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Patent # Description
US-1,011,5730 Three-dimensional memory device containing structurally reinforced pedestal channel portions and method of...
A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a semiconductor surface, a...
US-1,011,5729 Anti-fuse nonvolatile memory devices employing lateral bipolar junction transistors as selection transistors
An anti-fuse nonvolatile memory device includes an anti-fuse memory cell and a bipolar junction transistor. The anti-fuse, memory cell has a first terminal and...
US-1,011,5728 Laser spike annealing for solid phase epitaxy and low contact resistance in an SRAM with a shared PFET and NFET...
Embodiments are directed to a method of forming a semiconductor device and resulting structures having a shared SRAM trench and a common contact having a low...
US-1,011,5727 Method for manufacturing a microelectronic circuit and corresponding microelectronic circuit
The invention relates to a method for manufacturing a microelectronic circuit. A substrate is provided. A source contact, a bulk contact and a drain contact are...
US-1,011,5726 Method and system for forming memory fin patterns
Techniques disclosed herein, provide a method and fabrication structure for accurately increasing feature density for creating high-resolution features and also...
US-1,011,5725 Structure and method for hard mask removal on an SOI substrate without using CMP process
A hard mask material is removed from an SOI substrate without using a chemical mechanical polish (CMP) process. A blocking material is deposited on a hard mask...
US-1,011,5724 Double diffusion break gate structure without vestigial antenna capacitance
A double diffusion break (DDB) gate structure is provided by removing the vestigial antenna to provide a space and the space is filled, at least in part, with...
US-1,011,5723 Complementary metal oxide semiconductor (CMOS) devices employing plasma-doped source/drain structures and...
Complementary metal oxide semiconductor (CMOS) devices employing plasma-doped source/drain structures and related methods are disclosed. In certain aspects, a...
US-1,011,5722 Semiconductor devices and methods for manufacturing the same
A semiconductor device and a method for manufacturing the same are disclosed. The method comprises forming active patterns on a substrate that includes first...
US-1,011,5721 Planar device on fin-based transistor architecture
Techniques are disclosed for forming a planar-like transistor device on a fin-based field-effect transistor (finFET) architecture during a finFET fabrication...
US-1,011,5719 Integrated circuits with resistor structures formed from MIM capacitor material and methods for fabricating same
Integrated circuits having resistor structures formed from a MIM capacitor material and methods for fabricating such integrated circuits are provided. In an...
US-1,011,5718 Method, apparatus, and system for metal-oxide-semiconductor field-effect transistor (MOSFET) with electrostatic...
Methods, apparatus, and systems relating to a MOSFET with ESD resistance, specifically, to a semiconductor device comprising a field-effect transistor (FET)...
US-1,011,5717 Electrostatic discharge protection structure and fabrication method thereof
A method is provided for fabricating an electrostatic discharge (ESD) protection structure. The method includes forming a substrate having a first region and a...
US-1,011,5716 Die bonding to a board
A method of bonding a plurality of die having first and second metal layers on a die surface to a board, comprising placing a first die onto a board comprising...
US-1,011,5715 Methods of making semiconductor device packages and related semiconductor device packages
Methods of fabricating a semiconductor device package may involve providing a fan out wafer including semiconductor-device-package locations at a base level....
US-1,011,5714 Semiconductor device and optical coupling device
According to one embodiment, a semiconductor device includes a first semiconductor element having a first surface, a second semiconductor element having a lower...
US-1,011,5713 Optoelectronic assembly and method of operating an optoelectronic assembly
An optoelectronic assembly includes at least one first component that emits first electromagnetic radiation and at least one first photosensitive component that...
US-1,011,5712 Electronic module
An electronic module is provided, which includes a first package and a second package stacked on the first package. The first package has an encapsulant and an...
US-1,011,5711 Vertical light emitting diode with magnetic back contact
A structure containing a vertical light emitting diode (LED) is provided. The vertical LED is present in an opening located in a display substrate, and the...
US-1,011,5710 Package including a plurality of stacked semiconductor devices, an interposer and interface connections
A package can include a number of stacked dynamic random access memory (DRAM) semiconductor devices and an interposer. Wirings can be formed in the interposer...
US-1,011,5709 Apparatuses comprising semiconductor dies in face-to-face arrangements
Some embodiments include an apparatus having a first chip and a second chip. Each of the first and second chips comprises a multilevel wiring structure and a...
US-1,011,5708 Semiconductor package having a redistribution line structure
A semiconductor package may include a first semiconductor chip having first bonding pads on a first active surface. The semiconductor package may include a...
US-1,011,5707 Adhesive film and semiconductor package using adhesive film
An adhesive film that can solve the problem of pickup defect and improve the yield rate of semiconductor packages. The adhesive film includes: (A) a...
US-1,011,5706 Semiconductor chip including a plurality of pads
A semiconductor chip including a plurality of input/output units includes: a plurality of additional pads disposed on a surface of the semiconductor chip,...
US-1,011,5705 Semiconductor package and manufacturing method thereof
A semiconductor package and manufacturing method thereof are disclosed and may include a first semiconductor device comprising a first bond pad on a first...
US-1,011,5704 Semiconductor device
A semiconductor device includes a first semiconductor chip having a first surface, a second surface on a side of the first semiconductor chip opposite to that...
US-1,011,5703 Semiconductor device and manufacturing method thereof
A semiconductor device includes a first semiconductor substrate, a second semiconductor substrate, a first metal layer located on the first semiconductor...
US-1,011,5702 Semiconductor chip for sensing temperature and semiconductor system including the same
In one example embodiment, a semiconductor system includes a first chip configured to generate first temperature information of the first chip, the first...
US-1,011,5701 Semiconductor device and method of forming conductive vias by backside via reveal with CMP
A semiconductor device has a semiconductor wafer and a conductive via formed through the semiconductor wafer. A portion of the semiconductor wafer is removed...
US-1,011,5700 Power module, electrical power conversion device, and driving device for vehicle
The object of the present invention is to compensate for a difference in threshold voltage between a plurality of switching devices incorporated in a power...
US-1,011,5699 Method for manufacturing wire bonding structure, wire bonding structure, and electronic device
A manufacturing method for a wire bonding structure of the present invention includes a step of preparing a wire made of Cu and a step of joining the wire to a...
US-1,011,5698 Method for direct adhesion via low-roughness metal layers
A method for assembling a first substrate and a second substrate via metal adhesion layers, the method including: depositing, on a surface of each of the first...
US-1,011,5697 Coupling element, integrated circuit device and method of fabrication therefor
A coupling element for providing external coupling to a semiconductor die within an integrated circuit package. The coupling element comprises a flexible...
US-1,011,5696 Electronic device and method for manufacturing the same
An electronic device is disclosed, which comprises: a first substrate; an adhesion layer disposed on the first substrate and comprising a condensation product...
US-1,011,5695 Solid-state imaging device
A solid-state imaging device encompasses a detector substrate having a first main-surface, on which a plurality of first lands are arranged in a matrix, and a...
US-1,011,5694 Electronic device, electronic device fabrication method, and electronic apparatus
An electronic device includes an electronic part including a first substrate having a group of first terminals over a first front surface and having a concavity...
US-1,011,5693 Solder layer of a semiconductor chip arranged within recesses
One semiconductor chip includes a substrate having insulation properties, a plurality of bump electrodes provided on one surface of the substrate, a plurality...
US-1,011,5692 Method of forming solder bumps
A method of forming solder bumps includes preparing a substrate having a surface on which a plurality of electrode pads are formed, forming a resist layer on...
US-1,011,5691 Module, method for manufacturing the same, and electronic device
A module, comprising an electronic component having a first electrode, a mounting board having a second electrode, a solder-bump configured to connect the first...
US-1,011,5690 Method of manufacturing micro pins and isolated conductive micro pin
A method of manufacturing micro pins includes forming a release layer over a substrate. A pattern layer is formed over the release layer, in which the pattern...
US-1,011,5689 Semiconductor device and method for manufacturing the same
According to one embodiment, a semiconductor device includes a first semiconductor substrate having a first wiring electrode on a first surface thereof, a first...
US-1,011,5688 Solder metallization stack and methods of formation thereof
A semiconductor device includes a contact metal layer disposed over a semiconductor surface of a substrate, a diffusion barrier layer disposed over the contact...
US-1,011,5687 Method of pattern placement correction
In one embodiment of the invention, a method for correcting a pattern placement on a substrate is disclosed. The method begins by detecting three reference...
US-1,011,5686 Semiconductor structure and fabricating method thereof
A method of fabricating a semiconductor structure includes: forming a conductive layer on a first insulating layer; etching a portion of the conductive layer to...
US-1,011,5685 Method of manufacturing a semiconductor structure
A method of manufacturing a semiconductor structure includes providing a transceiver, forming a molding to surround the transceiver, forming a plurality of...
US-1,011,5684 Semiconductor device
A semiconductor device includes a first semiconductor chip including a first plurality of wiring layers, and a first coil, a first bonding pad, and first dummy...
US-1,011,5683 Electrostatic discharge protection for antenna using vias
An integrated circuit device is formed to include a plurality of vias that connect an antenna to a ground reference. This configuration of the integrated...
US-1,011,5682 Erasable programmable non-volatile memory
An erasable programmable non-volatile memory includes a first transistor, a second transistor, an erase gate region and a metal layer. The first transistor...
US-1,011,5681 Compact three-dimensional memory device having a seal ring and methods of manufacturing the same
A semiconductor die includes a pair of first alternating stacks of first portions of insulating layers and electrically conductive layers located over a...
US-1,011,5680 Semiconductor memory device and method for manufacturing the same
According to an embodiment, a semiconductor memory device includes a substrate, a first stacked body, a columnar part, a second insulating film, and a second...
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