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Patent # Description
US-1,011,5679 Trench structure and method
A trench structure includes a top metal layer, a silicon carbide (SiC) layer on the top metal layer, a first passivation layer overlying the SiC layer, and a...
US-1,011,5678 Wire bond wires for interference shielding
Apparatuses relating generally to a microelectronic package having protection from interference are disclosed. In an apparatus thereof, a substrate has an upper...
US-1,011,5677 Vertical interconnects for self shielded system in package (SiP) modules
A system in package (SiP) is disclosed that uses an EMI shield to inhibit EMI or other electrical interference on the components within the SiP. A metal shield...
US-1,011,5676 Integrated circuit and method of making an integrated circuit
An integrated circuit and a method of making the same. The integrated circuit includes a semiconductor substrate. The integrated circuit also includes a...
US-1,011,5675 Packaged semiconductor device and method of fabricating a packaged semiconductor device
In accordance with some embodiments of the present disclosure, a packaged semiconductor device includes a first package structure, at least one outer conductive...
US-1,011,5674 Semiconductor device including electromagnetic interference (EMI) shielding layer and method for manufacturing...
According to one embodiment, in a method for manufacturing a semiconductor device, a semiconductor chip is provided on a first surface of a substrate having the...
US-1,011,5673 Embedded substrate package structure
Provided is an embedded substrate package structure, including, from top to bottom, a fourth dielectric layer, a second substrate, a chip with a fifth...
US-1,011,5672 Double-sided semiconductor package and dual-mold method of making same
A semiconductor device comprises a first conductive layer formed on a carrier over an insulating layer. A portion of the insulating layer is removed prior to...
US-1,011,5671 Incorporation of passives and fine pitch through via for package on package
This disclosure provides systems, methods and apparatus for glass via bars that can be used in compact three-dimensional packages, including package-on-packages...
US-1,011,5670 Formation of advanced interconnects including set of metal conductor structures in patterned dielectric layer
A pattern is provided in a dielectric layer. The pattern includes a set of features in the dielectric for a set of metal conductor structures. The set of...
US-1,011,5669 High density nonvolatile memory cell unit array
In a memory cell unit array, memory cell units each constituted of first wires, second wires, and a nonvolatile memory cell are arranged in a two-dimensional...
US-1,011,5668 Semiconductor package having a variable redistribution layer thickness
Semiconductor packages having variable redistribution layer thicknesses are described. In an example, a semiconductor package includes a redistribution layer on...
US-1,011,5667 Semiconductor device with an interconnection structure having interconnections with an interconnection density...
A semiconductor device includes a cell semiconductor pattern disposed on a semiconductor substrate. A semiconductor dummy pattern is disposed on the...
US-1,011,5666 Method for making a photolithography mask intended for the formation of contacts, mask and integrated circuit...
A method for making a photolithography mask for formation of electrically conducting contact pads between tracks of a metallization level and electrically...
US-1,011,5665 Semiconductor resistor structures embedded in a middle-of-the-line (MOL) dielectric
A resistor structure composed of a metal liner is embedded within a MOL dielectric material and is located, at least in part, on a surface of a doped...
US-1,011,5664 Display panel and display device
A display panel and a display device are provided. The display panel comprises a first substrate having a step area; a second substrate disposed opposite to the...
US-1,011,5663 3D semiconductor device and structure
A 3D semiconductor device, the device including: a first single crystal layer including a plurality of first transistors and a first metal layer, where the...
US-1,011,5662 Semiconductor device and method of forming a curved image sensor
A semiconductor device has a semiconductor die containing a base material having a first surface and a second surface with an image sensor area. A masking layer...
US-1,011,5661 Substrate-less discrete coupled inductor structure
Some novel features pertain to an inductor structure that includes a first inductor winding, a second inductor winding and a filler. The first inductor winding...
US-1,011,5660 Leadframe strip with vertically offset die attach pads between adjacent vertical leadframe columns
A leadframe strip for use in making leaded integrated circuit packages includes a plurality of integrally connected leadframes that each have a die attach pad...
US-1,011,5659 Multi-terminal device packaging using metal sheet
A solution for packaging a two terminal device, such as a light emitting diode, is provided. In one embodiment, a method of packaging a two terminal device...
US-1,011,5658 Semiconductor device
In a non-leaded type semiconductor device, a tab, tab suspension leads, and other leads are exposed to one surface of a seal member. A semiconductor element is...
US-1,011,5657 Dielectric heat path devices, and systems and methods using the same
Devices, systems, and methods for dissipating heat generated from an electrical current carrying device are provided herein. The disclosed concept provides a...
US-1,011,5656 Semiconductor device
Performance of a semiconductor device is improved. Graphene particles are mixedly added in a sealing resin covering a semiconductor chip. The graphene particles...
US-1,011,5655 Heat dissipation substrate and method for producing heat dissipation substrate
A heat dissipation substrate having a metallic layer with few defects on its surface is obtained by a process including the steps of: forming a metallic layer...
US-1,011,5654 Buried thermally conductive layers for heat extraction and shielding
An embodiment is a method and apparatus for heat extraction and shielding in multi-block semiconductor devices. A plurality of blocks stacked on each other is...
US-1,011,5653 Thermal dissipation through seal rings in 3DIC structure
A package includes a die, which includes a semiconductor substrate, a plurality of through-vias penetrating through the semiconductor substrate, a seal ring...
US-1,011,5652 Semiconductor device and semiconductor apparatus
A semiconductor device includes a power device and a temperature detection diode. The semiconductor device has a device structure configured to insulate between...
US-1,011,5651 Electronic component having a chip mounted on a substrate with a sealing resin and manufacturing method thereof
An electronic component includes a substrate that has a first principal surface and a second principal surface, a chip that includes a mounting surface on which...
US-1,011,5650 Die-on-interposer assembly with dam structure and method of manufacturing the same
A semiconductor package includes an interposer chip having a frontside, a backside, and a corner area on the backside defined by a first corner edge and a...
US-1,011,5649 External connection mechanism, semiconductor device, and stacked package
A semiconductor device encompasses a connecting base including a semiconductor substrate and a surface insulating-film on the semiconductor substrate, a...
US-1,011,5648 Fan-out semiconductor package and electronic device including the same
A fan-out semiconductor package and an electronic device including the same are provided. The fan-out semiconductor package includes a semiconductor chip; an...
US-1,011,5647 Non-vertical through-via in package
A package includes a device die, a through-via having a sand timer profile, and a molding material molding the device die and the through-via therein, wherein a...
US-1,011,5646 Semiconductor arrangement, semiconductor system and method of forming a semiconductor arrangement
A semiconductor arrangement is provided. The semiconductor arrangement may include an electrically conductive plate having a surface, a plurality of power...
US-1,011,5645 Repackaged reconditioned die method and assembly
A method is provided. The method includes one or more of removing one or more existing ball bonds from an extracted die, reconditioning die pads of the...
US-1,011,5644 Interposer manufacturing method
A plurality of interposers are made from a material substrate. The material substrate includes a glass substrate partitioned by a plurality of crossing division...
US-1,011,5643 Circuit and method for monolithic stacked integrated circuit testing
A method for testing a monolithic stacked integrated circuit (IC) is provided. The method includes receiving a layer of the IC. The layer has a first surface...
US-1,011,5642 Semiconductor devices comprising nitrogen-doped gate dielectric, and methods of forming semiconductor devices
Some embodiments include semiconductor devices having first transistors of a first channel type and having second transistors of a second channel type. The...
US-1,011,5641 Semiconductor arrangement, method of manufacturing the same electronic device including the same
There are provided a semiconductor arrangement, a method of manufacturing the same, and an electronic device including the semiconductor arrangement. According...
US-1,011,5640 Method of manufacturing integrated circuit device
A method of manufacturing an integrated circuit device includes providing a substrate with a pattern structure, the pattern structure including a plurality of...
US-1,011,5639 FinFET device and method of forming the same
A method may include depositing a first conductive material in an opening disposed between a first semiconductor structure and a second semiconductor structure,...
US-1,011,5638 Partially recessed channel core transistors in replacement gate flow
An integrated circuit containing MOS transistors with replacement gates may be formed with elevated LDD regions and/or recessed replacement gates on a portion...
US-1,011,5637 Method for fabricating auto-aligned interconnection elements for a 3D integrated circuit
Method for fabricating transistors for an integrated 3D circuit, comprising: a) forming, on a given level of transistors made in a first semiconductor layer:...
US-1,011,5636 Processing method for workpiece
A workpiece has a plurality of low-dielectric-constant insulation films and a metallic pattern stacked on a surface of a semiconductor substrate. Devices are...
US-1,011,5635 Method for filling a wafer via with solder
A wafer via solder filling device includes a solder bath comprising an accommodation space for accommodating a molten solder, with an open top, and an air...
US-1,011,5634 Semiconductor component having through-silicon vias and method of manufacture
A semiconductor component includes a semiconductor substrate having an opening A first dielectric liner having a first compressive stress is disposed in the...
US-1,011,5633 Method for producing self-aligned line end vias and related device
A method for producing self-aligned line end vias and the resulting device are provided. Embodiments include trench lines formed in a dielectric layer; each...
US-1,011,5632 Three-dimensional memory device having conductive support structures and method of making thereof
An alternating stack of insulating layers and sacrificial material layers is formed over a horizontal layer, which can be formed over a lower-interconnect-level...
US-1,011,5631 Semiconductor device
A semiconductor device provided with a plurality of kinds of transistors with different device structures suitable for functions of circuits is provided. The...
US-1,011,5630 Interconnect structure and method of forming the same
An interconnect structure and a method of forming an interconnect structure are disclosed. The interconnect structure includes a lower etch stop layer (ESL); a...
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