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Patent # Description
US-1,021,7733 Fast SCR structure for ESD protection
An ultra-low capacitance ESD protection device with an ultra-fast response time and a low turn-on voltage, and a high holding current. The device may include: a...
US-1,021,7732 Techniques for forming a compacted array of functional cells
Techniques are disclosed for forming a compacted array of functional cells using next-generation lithography (NGL) processes, such as electron-beam direct write...
US-1,021,7731 Method of producing optoelectronic modules and an assembly having a module
A method produces a plurality of optoelectronic modules, and includes: A) providing a metallic carrier assembly with a plurality of carrier units; B) applying a...
US-1,021,7730 Efficiently micro-transfer printing micro-scale devices onto large-format substrates
A method of making a micro-transfer printed system includes providing a source wafer having a plurality of micro-transfer printable source devices arranged at a...
US-1,021,7729 Apparatus for micro pick and bond
Embodiments of the invention include systems and methods for transferring micro LEDs. In an embodiment, the system for transferring micro LEDs, may include a...
US-1,021,7728 Semiconductor package and semiconductor process
A semiconductor package includes a first semiconductor die, a first encapsulant, a first redistribution layer, a second encapsulant and a patterned conductive...
US-1,021,7727 Semiconductor device and electronic apparatus including a first semiconductor chip including an insulated gate...
For example, a semiconductor device capable of achieving a high performance applicable to an SR motor is provided. The semiconductor device includes a chip...
US-1,021,7726 Stacked semiconductor dies including inductors and associated methods
Several embodiments of the present technology are directed to semiconductor devices, systems including semiconductor devices, and methods of making and...
US-1,021,7725 Microstructure modulation for metal wafer-wafer bonding
A three-dimensional (3D) bonded semiconductor structure is provided in which a first bonding oxide layer of a first semiconductor structure is bonded to a...
US-1,021,7724 Semiconductor package assembly with embedded IPD
The invention provides a semiconductor package assembly. The semiconductor package assembly includes a first semiconductor package including a first...
US-1,021,7723 Semiconductor package with improved bandwidth
A semiconductor chip package includes a first die and a second die. The first die and second die are coplanar and disposed in proximity to each other in a...
US-1,021,7722 Semiconductor packages having asymmetric chip stack structure
A semiconductor package may include first chip stack including first chips which are stacked on a package substrate and offset to form a first reverse stepwise...
US-1,021,7721 Dual-sided memory module with channels aligned in opposition
Memory packages, memory modules, and circuit boards are described. In an embodiment, single channel memory packages are mounted on opposite sides of a circuit...
US-1,021,7720 Multi-chip modules formed using wafer-level processing of a reconstitute wafer
Apparatuses and methods are described. This apparatus includes a bridge die having first contacts on a die surface being in a molding layer of a reconstituted...
US-1,021,7719 Semiconductor device assemblies with molded support substrates
Semiconductor device assemblies with molded support substrates and associated methods are disclosed herein. In one embodiment, a semiconductor device assembly...
US-1,021,7718 Method for wafer-level semiconductor die attachment
A wafer-level semiconductor die attachment method includes placing a semiconductor die of a plurality of semiconductor dies at an initial placement position to...
US-1,021,7717 Distribution of electronic circuit power supply potentials
An integrated circuit includes peripheral conductive pads interconnected by a peripheral conductive track within an integrated circuit chip. The integrated...
US-1,021,7716 Semiconductor package and method for fabricating the same
A method for fabricating a semiconductor is disclosed. A carrier substrate is provided. A redistribution layer (RDL) structure is formed on the carrier...
US-1,021,7715 Semiconductor device with a bump contact on a TSV comprising a cavity and method of producing such a...
The semiconductor device comprises a semiconductor substrate (1) with a main surface (10) and a further main surface (11) opposite the main surface, a TSV (3)...
US-1,021,7713 Semiconductor device attached to an exposed pad
The present disclosure provides for embodiments of packaged semiconductor devices. In one embodiment, a packaged semiconductor device for a die includes an...
US-1,021,7712 Semiconductor package and semiconductor process for manufacturing the same
A semiconductor package includes a substrate, a dielectric layer, at least one conductive pillar and an electrical device. The dielectric layer is disposed on...
US-1,021,7711 Semiconductor package and manufacturing method thereof
A semiconductor package includes a ground electrode formed on an upper surface of a substrate, a first electronic component disposed on the upper surface of the...
US-1,021,7710 Wiring board with embedded component and integrated stiffener, method of making the same and face-to-face...
A wiring board includes an electronic component laterally surrounded by a stiffener, and a third routing circuitry disposed beyond the space laterally...
US-1,021,7709 Fan-out semiconductor package
The present disclosure relates to a semiconductor package, and more particularly, to a fan-out semiconductor package in which connection terminals may extend...
US-1,021,7708 High bandwidth routing for die to die interposer and on-chip applications
Routing structures including signal routing between die areas is described. In an embodiment, routing structures include signal lines with a characteristic...
US-1,021,7707 Trench contact resistance reduction
A method is presented for forming a semiconductor device. The method includes forming source/drain over a semiconductor substrate, forming a sacrificial layer...
US-1,021,7706 Semiconductor constructions
Some embodiments include methods of forming electrically conductive lines. Photoresist features are formed over a substrate, with at least one of the...
US-1,021,7705 Semiconductor devices
A semiconductor device includes a first conductive element, a first insulating layer and a second insulating layer sequentially disposed on the first conductive...
US-1,021,7704 Method for simultaneous modification of multiple semiconductor device features
Various technologies for simultaneously making a plurality of modifications to a previously manufactured semiconductor are described herein. A mask layer is...
US-1,021,7703 Circuits for and methods of implementing an inductor and a pattern ground shield in an integrated circuit
An integrated circuit device is described. The integrated circuit device comprises a substrate; a plurality of metal routing interconnect layers; an inductor...
US-1,021,7701 Semiconductor device
A semiconductor device includes a package substrate having a first surface and a second surface. A semiconductor chip is provided on the first surface of the...
US-1,021,7700 Lead frame for integrated circuit device having J-leads and Gull Wing leads
A lead frame for a packaged integrated circuit (IC) device has alternating first and second leads that protrude from a package body in respective first and...
US-1,021,7699 Preformed lead frame
A preformed lead frame includes a plurality of lead frame units and intersecting cutting paths extending between two adjacent rows of said lead frame units, and...
US-1,021,7698 Die attachment for packaged semiconductor device
A method for forming a packaged semiconductor device includes attaching a first major surface of a semiconductor die to a plurality of protrusions extending...
US-1,021,7697 Semiconductor device and lead frame with high density lead array
A semiconductor device includes a lead frame having leads arranged in an array that has columns extending in a first direction and rows extending in a second...
US-1,021,7696 Non-bridging contact via structures in proximity
A first photoresist layer is patterned with a first pattern that includes an opening in a region between areas of two adjacent via holes to be formed. The...
US-1,021,7695 Connector block with two sorts of through connections, and electronic device comprising a connector block
An electronic device comprising a semiconductor package having a first main surface region and a second main surface region and comprising a semiconductor chip...
US-1,021,7693 Methods and systems for high voltage component cooling in electric vehicle for fast charge
Methods and systems are disclosed for controlling heat within a junction box. The disclosure relates to the use of phase change materials to manage heat...
US-1,021,7692 Heat transfer device for high heat flux applications and related methods thereof
A device and related method that provides a two-phase heat transfer device with a combination of enhanced evaporation and increase cooling capacity. A recess...
US-1,021,7691 Heat spreader with optimized coefficient of thermal expansion and/or heat transfer
Methods, systems and an apparatus relating to a heat spreader to be coupled to a heat source having a heat source coefficient of thermal expansion (HS CTE), the...
US-1,021,7690 Semiconductor module that have multiple paths for heat dissipation
A semiconductor module includes a substrate, first and second wirings on the substrate, a semiconductor package disposed on the first wiring and having a pair...
US-1,021,7689 Semiconductor integrated circuit device and method for manufacturing the same
A semiconductor integrated circuit device includes: an insulating substrate; a via which penetrates through the insulating substrate; a first metal layer...
US-1,021,7688 Electronic component having a heat-sink thermally coupled to a heat-spreader
An electronic component includes one or more semiconductor dice embedded in a first dielectric layer, a heat-spreader embedded in a second dielectric layer and...
US-1,021,7687 Semiconductor device and manufacturing method thereof
A semiconductor device includes a semiconductor substrate, a conductive pad over the semiconductor substrate, a conductor over the conductive pad, a polymeric...
US-1,021,7686 Air-cavity package with enhanced package integration level and thermal performance
The present disclosure relates to an air-cavity package, which includes a bottom substrate, a top substrate, a perimeter wall, a bottom electronic component, a...
US-1,021,7685 Air-cavity package with dual signal-transition sides
The present disclosure relates to an air-cavity package, which includes a bottom substrate, a top substrate, a perimeter wall, a bottom electronic component,...
US-1,021,7684 Resin molding and sensor device
A resin molding includes a semiconductor element, a circuit board, and a resin. A conductor connected to the semiconductor element is formed on the circuit...
US-1,021,7683 Mounted semiconductor module with a mold resin portion
A semiconductor module is provided in which a semiconductor element is mounted and a plurality of outside connecting modules are drawn from a side of a mold...
US-1,021,7682 Time temperature monitoring system
A time temperature monitoring system and method for use with a microchip or similar structure. A disclosed system includes: a substrate having an active region;...
US-1,021,7681 Gases for low damage selective silicon nitride etching
Silicon nitride plasma etching processes are disclosed that minimize the SiN roughness layer on a substrate having a SiN layer thereon by simultaneously...
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