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Patent # Description
US-1,023,6276 Semiconductor device including vertically integrated groups of semiconductor packages
A semiconductor device is disclosed including at least first and second vertically stacked and interconnected groups of semiconductor packages. The first and...
US-1,023,6275 Stacking integrated circuits containing serializer and deserializer blocks using through silicon via
A die stack having a second die is stacked vertically on top of a first die. A first plurality of test pads is located along a first edge of the first die. A...
US-1,023,6274 Semiconductor device with metal patterns having convex and concave sides
Reduction in reliability of a semiconductor device is suppressed. A semiconductor device includes a plurality of metal patterns formed on a ceramic substrate,...
US-1,023,6273 Packaging structure including interconnecs and packaging method thereof
A packaging structure and a packaging method are provided. The packaging structure includes a carrier semiconductor structure including a carrier substrate, a...
US-1,023,6272 Cu alloy core bonding wire with Pd coating for semiconductor device
A bonding wire for a semiconductor device includes a Cu alloy core material and a Pd coating layer formed on a surface thereof, and the boding wire contains one...
US-1,023,6270 Interposer and semiconductor module for use in automotive applications
An interposer of silicon for use in a semiconductor module, wherein the interposer has a top side serving for arrangement of functional semiconductor and an...
US-1,023,6269 Semiconductor device having semiconductor chip with large and small irregularities on upper and lower side...
A semiconductor device has a semiconductor chip adhesively bonded to a die pad. An area having large irregularities is formed on an upper side surface of the...
US-1,023,6268 Robust pillar structure for semicondcutor device contacts
Methods and systems for a robust pillar structure for a semiconductor device contacts are disclosed, and may include processing a semiconductor wafer comprising...
US-1,023,6267 Methods of forming flip chip systems
Forming the chip attachment system includes obtaining a chip having a bump core on a die. The method also includes obtaining an intermediate structure having a...
US-1,023,6266 Element chip manufacturing method
An element chip manufacturing method includes a preparation process of preparing a substrate which includes a first surface having an exposed bump and a second...
US-1,023,6265 Semiconductor chip and method for forming a chip pad
A semiconductor chip with different chip pads and a method for forming a semiconductor chip with different chip pads are disclosed. In some embodiments, the...
US-1,023,6264 Wireless IC device, resin molded body comprising same, communication terminal apparatus comprising same, and...
A wireless IC device includes an element body including first and second principal surfaces, an RFIC element buried in the element body, and an antenna coil...
US-1,023,6263 Methods and structures for mitigating ESD during wafer bonding
One method includes positioning a front side of a first substrate opposite a side of a second substrate, the first substrate comprising an ESD mitigation...
US-1,023,6262 System and method for protecting an integrated circuit (IC) device
Embodiments of the invention provide a system for protecting an integrated circuit (IC) device from attacks, the IC device (100) comprising a substrate (102)...
US-1,023,6261 Electronic package and method for fabricating the same
An electronic package is provided, which includes: a substrate; an electronic component and a shielding member disposed on the substrate; an encapsulant formed...
US-1,023,6260 Shielded package with integrated antenna
A semiconductor structure includes a packaged semiconductor device having at least one device, a conductive pillar, an encapsulant over the at least one device...
US-1,023,6259 Mark, method for forming same, and exposure apparatus
A mark forming method includes: forming recessed portion on a mark formation area of a substrate; coating the recessed portion with a polymer layer containing a...
US-1,023,6258 Method of manufacturing a semiconductor device with epitaxial layers and an alignment mark
An alignment mark in a process surface of a semiconductor layer includes a groove with a minimum width of at least 100 .mu.m and a vertical extension in a range...
US-1,023,6257 Cobalt top layer advanced metallization for interconnects
A method for constructing an advance conductor structure is described. A pattern is provided in a dielectric layer in which a set of features are patterned for...
US-1,023,6256 Pre-spacer self-aligned cut formation
Methods of forming self-aligned cuts and structures formed with self-aligned cuts. A dielectric layer is formed on a metal hardmask layer, and a mandrel is...
US-1,023,6255 Contact having self-aligned air gap spacers
A semiconductor device includes a semiconductor substrate, and a dielectric layer on an upper surface of the semiconductor substrate. A contact stack is formed...
US-1,023,6254 Semiconductor memory device
A semiconductor memory device includes first and second insulating plates, a stacked body provided between the first insulating plate and the second insulating...
US-1,023,6253 Self-aligned local interconnect technology
A self-aligned interconnect structure includes a fin structure patterned in a substrate; an epitaxial contact disposed over the fin structure; a first metal...
US-1,023,6252 Hybrid subtractive etch/metal fill process for fabricating interconnects
In one example, a method for fabricating an integrated circuit includes patterning a layer of a first conductive metal, via a subtractive etch process, to form...
US-1,023,6251 Method for providing electrical antifuse including phase change material
An antifuse structure including a first electrode that is present in at a base of the opening in the dielectric material. The antifuse structure further...
US-1,023,6250 Method for providing electrical antifuse including phase change material
An antifuse structure including a first electrode that is present in at a base of the opening in the dielectric material. The antifuse structure further...
US-1,023,6249 Anti-fuse device and memory device including the same
An anti-fuse device includes a program transistor and a read transistor. The program transistor executes a program via insulation breakdown of a gate insulating...
US-1,023,6248 Semiconductor device and manufacturing method thereof
The manufacturing method of a semiconductor device can improve the mechanical strength of a pad more than before, and suppress the occurrence of a crack. The...
US-1,023,6247 Isolation device
An isolation system, isolation device, and Integrated Circuit are disclosed. The isolation system is described to include an integrated circuit chip having a...
US-1,023,6246 Semiconductor devices and methods for forming a semiconductor device
A semiconductor device includes a crack propagation prevention structure. The crack propagation prevention structure is located at an edge region of a wiring...
US-1,023,6245 Package substrate with embedded circuit
A package substrate with embedded circuit is disclosed. The package substrate comprises a redistribution layer, the redistribution layer comprises a plurality...
US-1,023,6244 Semiconductor device and production method therefor
Provided is a semiconductor device having a wiring structure on a semiconductor element and capable of securing high quality and high reliability in response to...
US-1,023,6243 Electronic component, electronic module, manufacturing method therefor, and electronic apparatus
An electronic component includes an electronic device, a mounting member for mounting the electronic device and having a first connecting portion electrically...
US-1,023,6242 Chip package and package substrate
A package substrate is provided. The package substrate includes a dielectric layer and a passive component embedded in the dielectric layer and contacting the...
US-1,023,6240 Low loss substrate for high data rate applications
In one or more embodiments, a substrate includes a patterned conductive layer and a reference layer. The patterned conductive layer includes a pair of first...
US-1,023,6239 Apparatus and semiconductor structure including a multilayer package substrate
An apparatus includes a multilayer package substrate having a plurality of layers. The apparatus also includes a first heat sink disposed over the package...
US-1,023,6238 Semiconductor device
A first semiconductor device includes: a first wiring layer including a first interlayer insulating film, a first electrode pad, and a first dummy electrode,...
US-1,023,6237 Bipolar transistor, semiconductor device, and bipolar transistor manufacturing method
Disconnection of a base line is suppressed even when a short-side direction of a collector layer is parallel to crystal orientation [011]. A bipolar transistor...
US-1,023,6236 Heterojunction semiconductor device for reducing parasitic capacitance
A semiconductor device includes an active layer, a source electrode, a drain electrode, a gate electrode, a first insulating layer, a first source pad, and a...
US-1,023,6235 Thermally enhanced semiconductor package having field effect transistors with back-gate feature
The present disclosure relates to a thermally enhanced semiconductor package having field effect transistors (FETs) with a back-gate feature. The thermally...
US-1,023,6234 Chip on film package
A chip on film package includes a base film, a patterned circuit layer, a solder resist layer, a chip and a graphite sheet. The base film includes a first...
US-1,023,6233 Heat spreaders with integrated preforms
Embodiments of heat spreaders with integrated preforms, and related devices and methods, are disclosed herein. In some embodiments, a heat spreader may include:...
US-1,023,6232 Dual-use thermal management device
Various thermal management devices for providing thermal management of integrated circuit chips are disclosed. In one aspect, a thermal management device is...
US-1,023,6231 Semiconductor device
A semiconductor device includes a lead frame; a circuit board located on the lead frame; a power device that includes a switching element and is mounted on the...
US-1,023,6230 Electronic device and method for manufacturing the same
In an electronic device, an inner lead of a signal terminal includes a base member, and a film on a surface of the inner lead adjacent to a bonding surface. The...
US-1,023,6229 Stacked silicon package assembly having conformal lid
A chip package assembly and method for fabricating the same are provided which utilize a conformal lid to improve the chip package assembly from deformation. In...
US-1,023,6228 Electronic component mounting board, electronic device, and electronic module
An electronic component mounting board reduces shadows produced along its perimeter to improve the mountability of an electronic device and an electronic...
US-1,023,6227 Electronic package and fabrication method thereof
An electronic package is provided, including a circuit portion, an electronic element disposed on the circuit portion and a lid member disposed on the circuit...
US-1,023,6226 In-situ calibration structures and methods of use in semiconductor processing
Systems and methods of in-situ calibration of semiconductor material layer deposition and removal processes are disclosed. Sets of test structures including one...
US-1,023,6225 Method for PECVD overlay improvement
The present disclosure generally relates to a method for performing semiconductor device fabrication, and more particularly, to improvements in lithographic...
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