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Patent # Description
US-1,023,6224 Apparatus and method for reducing wafer warpage
An apparatus and a method for reducing wafer warpage are provided. The method includes positioning a mold wafer structure on a stage. The mold wafer structure...
US-1,023,6223 Substrate processing method, program, apparatus and system to determine substrate processing result
Disclosed is a substrate processing method. The substrate processing method includes: a first acquisition step of acquiring a first processing condition in a...
US-1,023,6222 System and method for measuring substrate and film thickness distribution
The system includes a dual interferometer sub-system configured to measure flatness across a substrate. The system includes a mass sensor configured to measure...
US-1,023,6221 Forming an isolation barrier in an isolator
Integrated digital isolators comprise a first transformer coil or capacitor plate mounted on an integrated circuit substrate, and separated from a second...
US-1,023,6220 Fin field-effect transistor device and method
A method includes removing a first portion of a dummy gate structure over a first fin while keeping a second portion of the dummy gate structure over a second...
US-1,023,6219 VFET metal gate patterning for vertical transport field effect transistor
Forming a PFET work function metal layer on a p-type field effect transistor (PFET) fin in a PFET region and on an n-type field effect transistor (NFET) fin in...
US-1,023,6218 Methods, apparatus and system for forming wrap-around contact with dual silicide
At least one method, apparatus and system disclosed herein involves forming semiconductor devices comprising dual silicides in contacts to FinFETs. The...
US-1,023,6217 Stacked field-effect transistors (FETs) with shared and non-shared gates
A semiconductor device includes a plurality of stacked gate regions spaced apart from each other on a substrate, a plurality of first epitaxial source/drain...
US-1,023,6216 Method for manufacturing a semiconductor device having a fin located on a substrate
The present disclosure relates to the technical field of semiconductor processes, and discloses a semiconductor device and a manufacturing method therefor. The...
US-1,023,6215 Methods of forming gate contact structures and cross-coupled contact structures for transistor devices
One illustrative method disclosed includes, among other things, forming an initial gate-to-source/drain (GSD) contact structure and an initial CB gate contact...
US-1,023,6214 Vertical transistor with variable gate length
A method of forming a vertical transistor includes forming a first pair of fins on a substrate; forming a second pair of fins on the substrate; forming a first...
US-1,023,6213 Gate cut structure with liner spacer and related method
A gate cut structure for finFETs, and a related method, are disclosed. The gate cut structure separates and electrically isolates an end of a first metal gate...
US-1,023,6212 Source and drain epitaxial semiconductor material integration for high voltage semiconductor devices
A method of forming a semiconductor device that includes providing a first set of fin structures having a first pitch, and a second set of fin structure having...
US-1,023,6211 Method of manufacturing vertical memory devices
A vertical memory device may include a plurality of word lines spaced apart in a first direction, each extending in a second direction perpendicular to the...
US-1,023,6210 Direct bonding method
The method is carried out of a first substrate having a first layer made of a first material with a second substrate having a second layer made of a second...
US-1,023,6209 Passive components in vias in a stacked integrated circuit package
Integrated passive component in a stacked integrated circuit package are described. In one embodiment an apparatus has a substrate, a first die coupled to the...
US-1,023,6208 Semiconductor package structure and method of manufacturing the same
The present disclosure relates to a semiconductor package structure and a method of manufacturing the same. The semiconductor package structure includes a...
US-1,023,6207 Hydrogenation and nitridization processes for reducing oxygen content in a film
Embodiments described herein generally relate to a sequential hydrogenation and nitridization process for reducing interfacial and bulk O atoms in a conductive...
US-1,023,6206 Interconnects with hybrid metallization
Structures for interconnects and methods for forming interconnects. A dual-damascene opening is formed in a dielectric layer and a first liner is formed on the...
US-1,023,6205 Thin film and method for manufacturing thin film
The present invention provides a kind of thin film and a fabrication method of thin films. The method comprises implanting ions under the surface of the...
US-1,023,6204 Semiconductor processing system
The semiconductor processing system includes a reactor chamber that has an upper wall and a lower wall. A hold member is disposed in the reactor chamber to hold...
US-1,023,6203 Lithographic apparatus substrate table and method of loading a substrate
A lithographic apparatus substrate table comprises a plurality of first projections, whereby the first projections define a first substrate supporting plane and...
US-1,023,6202 System and method for adhering a semiconductive wafer to a mobile electrostatic carrier through a vacuum
A mobile electrostatic carrier (MESC) provides a structural platform to temporarily bond a semiconductive wafer and can be used to transport the semiconductive...
US-1,023,6201 Wafer carrier for smaller wafers and wafer pieces
Embodiments described herein relate to an apparatus and method for securing and transferring substrates. A substrate carrier, having one or more electrostatic...
US-1,023,6200 Exposure device and substrate processing apparatus
With a cover member being located directly upward of an opening of a casing, a substrate in a horizontal attitude is carried into a gap between the cover member...
US-1,023,6199 Substrate processing method and substrate processing apparatus
A substrate processing method comprises: an execution step of executing the first processing for the plurality of substrates, and executing the second...
US-1,023,6198 Methods for the continuous processing of substrates
Methods of processing a plurality of substrates using a processing chamber with bottom and top openings and a plurality of processing slots are provided. A...
US-1,023,6197 Processing system containing an isolation region separating a deposition chamber from a treatment chamber
An apparatus and method for processing a substrate in a processing system containing a deposition chamber, a treatment chamber, and an isolation region,...
US-1,023,6196 Substrate processing system
A substrate processing system is provided. The substrate processing system includes: a first transfer apparatus; at least two first accommodating units...
US-1,023,6195 Method for transferring device
A method for transferring a device includes the following steps: forming a pliable adhesive layer on a carrier substrate; placing the device over the pliable...
US-1,023,6194 Supporting unit and substrate treatment apparatus
Provided is a supporting unit supporting a substrate. The supporting unit includes a body including a plurality of heating regions and disposed with the...
US-1,023,6193 Substrate supports with multi-layer structure including independent operated heater zones
A substrate support is provided, is configured to support a substrate in a plasma processing chamber, and includes first, second and third insulative layers,...
US-1,023,6192 Liquid processing apparatus, liquid processing method, and storage medium
A liquid processing apparatus of the present disclosure holds and rotate a substrate in a substrate holding unit, ejects an etching liquid while moving a main...
US-1,023,6191 Wafer drying apparatus and method for drying a wafer
A wafer drying apparatus includes air supply unit having first and second air supply tube provided at respective first and second front-surface side of wafer,...
US-1,023,6189 Adhesive-bonded thermal interface structures for integrated circuit cooling
A heat sink can be attached to a heat-producing electronic device by aligning an adhesive material to a surface of the heat sink, applying the adhesive material...
US-1,023,6188 Electrostatic nozzle, discharge apparatus, and method for manufacturing semiconductor module
An electrostatic nozzle includes a first pipe, a second pipe, and a third pipe. The first pipe is configured of a conductor. Voltage is applied on the first...
US-1,023,6187 Semiconductor package and method for fabricating base for semiconductor package
The invention provides a semiconductor package and a method for fabricating a base for a semiconductor package. The semiconductor package includes a base. The...
US-1,023,6186 Methods for dry hard mask removal on a microelectronic substrate
The disclosure relates to methods for a multi-step plasma process to remove metal hard mask layer from an underlying hard mask layer that may be used to...
US-1,023,6185 Method of forming patterns for semiconductor device
A method of forming patterns for a semiconductor device includes preparing a hardmask composition including a carbon allotrope, a spin-on hardmask (SOH)...
US-1,023,6184 Porous tin oxide films
Initial film layers prepared from tin(II) chloride spontaneously generate open cavities when the initial film layers are thermally cured to about 400.degree. C....
US-1,023,6183 Monolithic integration of semiconductor materials
A method for forming a semiconductor structure by bonding a donor substrate to a carrier substrate is disclosed herein. The donor substrate may include a...
US-1,023,6182 Conformal amorphous carbon for spacer and spacer protection applications
A method of forming a nitrogen-doped amorphous carbon layer on a substrate in a processing chamber is provided. The method generally includes depositing a...
US-1,023,6181 Manufacturing system and method for forming a clean interface between a functional layer and a two-dimensional...
A manufacturing system and a method for forming a clean interface between a functional layer and a 2D layered semiconductor are provided herein. In the steps of...
US-1,023,6180 Method of making semiconductor integrated circuit device relating to resistance characteristics
A semiconductor integrated circuit device may include a structure, a first capping layer, a channel layer and a second capping layer. The structure may have an...
US-1,023,6179 Method for fabricating semiconductor device
A method for forming an epitaxial layer on a substrate is disclosed. The method includes the steps of: providing a substrate into a chamber; injecting a...
US-1,023,6178 Gallium nitride nanowire based electronics
GaN based nanowires are used to grow high quality, discreet base elements with c-plane top surface for fabrication of various semiconductor devices, such as...
US-1,023,6177 Methods for depositing a doped germanium tin semiconductor and related semiconductor device structures
A method for depositing a germanium tin (Ge.sub.1-xSn.sub.x) semiconductor is disclosed. The method may include; providing a substrate within a reaction...
US-1,023,6176 Robust high performance low hydrogen silicon carbon nitride (SiCNH) dielectrics for nano electronic devices
A method for depositing a dielectric layer that includes introducing a substrate into a process chamber of a deposition tool; and heating the substrate to a...
US-1,023,6175 Liquid chemical for forming protecting film
Disclosed is a liquid chemical for forming a water-repellent protecting film on a wafer. The liquid chemical is a liquid chemical containing a ...
US-1,023,6174 Lumen maintenance in fluorescent lamps
A fluorescent lamp, including a vitreous portion of the fluorescent lamp comprising a vitreous envelope filled with a working gas mixture, the vitreous envelope...
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