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Patent # Description
US-1,023,6071 Dual-bit ROM cell with virtual ground line and programmable metal track
A read-only memory (ROM) device includes memory cells, bit-line pairs, a virtual ground line, and a programmable metal track. The memory cells are arranged in...
US-1,023,6070 Read level tracking and optimization
Systems and methods for read level tracking and optimization are described. Pages from a wordline of a flash memory device read and the raw page data read from...
US-1,023,6069 Word line read disturb error reduction through fine grained access counter mechanism
An apparatus is described. The apparatus includes a storage device having multiple non volatile memory chips and controller circuitry. The controller circuitry...
US-1,023,6068 Sensing amplifier comprising bias circuitry coupled to bit line and dummy bitline for performing read operation...
The present invention relates to an improved sensing amplifier and related method for use in read operations in flash memory devices. In one embodiment, a...
US-1,023,6067 State-dependent read voltage threshold adaptation for nonvolatile memory
A controller adapts the read voltage thresholds of a memory unit in a non-volatile memory. In one embodiment, the controller determines, based on statistics for...
US-1,023,6066 Method of managing semiconductor memories, corresponding interface, memory and device
A non-volatile data memory space for a range of user addresses is provided by means of a range of non-volatile flash memory locations for writing data. The...
US-1,023,6065 Nonvolatile memory device including multi-plane structure
A nonvolatile memory device includes a memory cell array having a first plane and a second plane and an address decoder connected to the first plane through...
US-1,023,6064 Semiconductor memory device and operation method thereof
A semiconductor memory device includes a cell string and a peripheral circuit. The cell string includes a plurality of memory cells coupled between a common...
US-1,023,6063 Split memory bank
A split memory bank may comprise a number of memory matrices forming a memory bank and a shift register in which the shift register physically separates the...
US-1,023,6062 Processor
According to one embodiment, a processor includes a core controlling processing data, a cache data area storing the processing data as cache data in a...
US-1,023,6061 Resistive random access memory having charge trapping layer, manufacturing method thereof, and operation thereof
A resistive random access memory (RRAM) including a first electrode, a second electrode, and a charge trapping layer is provided. The second electrode is...
US-1,023,6060 Nonvolatile memory device
According to one embodiment, a nonvolatile memory device includes word lines, bit lines, resistance change memory elements, each selectively exhibiting a low or...
US-1,023,6059 System and method for performing memory operations on RRAM cells
A resistive RAM (RRAM) device has a bit line, a word line, a source line carrying a bias voltage that is a substantially static and non-negative voltage, an...
US-1,023,6058 Non-volatile semiconductor memory device adapted to store a multi-valued data in a single memory cell
A non-volatile semiconductor memory device includes an electrically data rewritable non-volatile semiconductor memory cell and a write circuit for writing data...
US-1,023,6057 Memory cells and methods for writing data to memory cells
Semiconductor memory devices and methods for writing data in memory cells are provided. An exemplary method for writing data in a memory cell includes providing...
US-1,023,6056 Volatile memory device and system-on-chip including the same
A volatile memory device includes a memory cell array configured to be supplied with a first power supply voltage through a first power supply line, and...
US-1,023,6055 Memory element write-assist circuitry with dummy bit lines
Integrated circuits with memory elements are provided. In particular, a group of random-access memory cells may be coupled to first and second data lines via...
US-1,023,6054 Method and system for systematic read retry flow in solid state memory using a retry table
In general, embodiments of the technology relate to improving read performance of solid-state storage by using decoding parameters deemed particularly suitable...
US-1,023,6053 Method and circuit device incorporating time-to-transition signal node sensing
Methods, devices, and systems are disclosed that generally perform a time delay determination of a voltage change on a signal node to determine a corresponding...
US-1,023,6052 Current sense amplifiers, memory devices and methods
A current sense amplifier may include one or more clamping circuits coupled between differential output nodes of the amplifier. The clamping circuits may be...
US-1,023,6051 Memory controller
A memory controller component includes transmit circuitry and adjusting circuitry. The transmit circuitry transmits a clock signal and write data to a DRAM, the...
US-1,023,6050 Optimizing data approximation analysis using low power circuitry
Optimizing data approximation analysis using low power circuitry including receiving a first set of data results and a second set of data results; charging a...
US-1,023,6049 Power reduction for a sensing operation of a memory cell
Methods, systems, and devices for operating a ferroelectric memory cell or cells are described. A memory device may leverage non-volatile memory properties of a...
US-1,023,6048 AC current write-assist in orthogonal STT-MRAM
Methods and structures useful for magnetoresistive random-access memory (MRAM) are disclosed. The MRAM device has a magnetic tunnel junction stack having a...
US-1,023,6047 Shared oscillator (STNO) for MRAM array write-assist in orthogonal STT-MRAM
Methods and structures useful for magnetoresistive random-access memory (MRAM) are disclosed. The MRAM device has plurality of magnetic tunnel junction (MTJ)...
US-1,023,6046 Method of propagating magnetic domain wall in magnetic devices
The disclosed technology generally relates to magnetic devices, and more particularly to magnetic devices configured to generate a stream of domain walls...
US-1,023,6045 Semiconductor memory device having detection clock patterns phase-inverted from each other and detection clock...
A clock pattern generating method of a semiconductor memory device is provided. The method includes generating the same clock pattern through a plurality of...
US-1,023,6044 Memory system
A memory system includes a semiconductor memory and a controller. The controller is configured to perform a read operation on the semiconductor memory in...
US-1,023,6043 Emulated multiport memory element circuitry with exclusive-OR based control circuitry
Integrated circuits may include memory element circuitry. The memory element circuitry may include multiple dual-port memory elements that are controlled to...
US-1,023,6042 Clocked commands timing adjustments method in synchronous semiconductor integrated circuits
A method in a clocked integrated circuit receiving an input clock signal having a clock frequency and a command signal for accessing a memory element in the...
US-1,023,6041 Determining a state of a memory cell
A method is suggested for determining a state of a memory cell via a sense amplifier the method including applying a first signal to the sense amplifier;...
US-1,023,6040 Two-step data-line precharge scheme
Apparatus and methods are disclosed, including an apparatus having a first transistor configured to be coupled to a first bit line, and a control circuit...
US-1,023,6039 Apparatuses and methods for chip identification in a memory package
Apparatuses, methods, memory packages, and semiconductor chips are disclosed. An example apparatus includes a semiconductor chip including a layer...
US-1,023,6038 Bank to bank data transfer
The present disclosure includes apparatuses and methods for bank to bank data transfer. An example apparatus includes a plurality of banks of memory cells, an...
US-1,023,6037 Data transfer in sensing components
Examples of the present disclosure provide apparatuses and methods related to performing a loop structure for operations performed in memory. An example...
US-1,023,6036 Sense amplifier signal boost
Apparatuses for signal boost are disclosed An example apparatus includes: first and second digit lines coupled to memory cells; a sense amplifier including:...
US-1,023,6035 DRAM memory device adjustable refresh rate method to alleviate effects of row hammer events
The present disclosure provides a dynamic random access memory (DRAM). The DRAM includes a refresh unit, an accessing device and a refresh device. The refresh...
US-1,023,6034 Memory module battery backup
Examples disclosed herein relate to dual in-line memory module (DIMM) battery backup. Some examples disclosed herein describe systems that include a backup...
US-1,023,6033 Memory device and semiconductor device
An object of one embodiment of the present invention is to propose a memory device in which a period in which data is held is ensured and memory capacity per...
US-1,023,6032 Mass data storage system with non-volatile memory modules
A mass data storage system, which comprises: a controller for issuing and receiving signals to carry out memory operations; a motherboard comprising at least...
US-1,023,6031 Timeline reconstruction using dynamic path estimation from detections in audio-video signals
A dynamic path estimation method reconstructs a program timeline in real time from an incoming stream of audio or visual content in which watermark payloads are...
US-1,023,6030 Recording medium, playback method, and playback device
A playback method of reading out and playing streams from a recording medium is provided, in which are recorded a stream file including a first luminance video...
US-1,023,6029 Video editing system with map-oriented replay feature
A video editing system that enables replay of activities performed by one or more objects of interest, and displayed on a map. The editing system receives a...
US-1,023,6028 Automatic generation of video from structured content
Device for providing a playable sequence in renderable manner comprises: a providing unit for providing defined functions, said functions for applying playable...
US-1,023,6027 Data storage using light of spatially modulated phase and polarization
An optical data-storage system comprises a laser, an imaging optic, and associated computer logic. The laser is configured to emit a pulsed wavefront having...
US-1,023,6026 Thermal barrier layers and seed layers for control of thermal and structural properties of HAMR media
Thermal barrier layers and seed layers for control of thermal and structural properties of heat assisted magnetic recording (HAMR) media are provided. One such...
US-1,023,6025 Evaluation method of magnetic tape and manufacturing method of magnetic tape
Provided are an evaluation method of a magnetic tape, in which the magnetic tape which is an evaluation target includes a magnetic layer including a servo...
US-1,023,6024 Segmented magnetic recording write head for detection-based servo pattern writing
An apparatus-implemented method according to one embodiment includes passing a magnetic recording tape over a plurality of modules having write transducers....
US-1,023,6023 Planar mono coil for two stage head actuator
An apparatus, according to one embodiment, includes: a head carriage assembly having a beam for coupling to a magnetic head, and an actuator assembly coupled to...
US-1,023,6022 Multi-layer PZT microactuator having a poled but inactive PZT constraining layer
A multi-layer piezoelectric microactuator assembly has at least one poled and active piezoelectric layer and one poled but inactive piezoelectric layer. The...
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