Easy To Use Patents Search & Patent Lawyer Directory

At Patents you can conduct a Patent Search, File a Patent Application, find a Patent Attorney, or search available technology through our Patent Exchange. Patents are available using simple keyword or date criteria. If you are looking to hire a patent attorney, you've come to the right place. Protect your idea and hire a patent lawyer.

Searching:





Search by keyword, patent number, inventor, assignee, city or state:




Patent # Description
US-1,024,2969 Semiconductor package comprising a transistor chip module and a driver chip module and a method for fabricating...
A semiconductor package includes a first semiconductor module including a plurality of semiconductor transistor chips and a first encapsulation layer disposed...
US-1,024,2968 Interconnect structure and semiconductor structures for assembly of cryogenic electronic packages
A cryogenic electronic package includes at least two superconducting and/or conventional metal semiconductor structures. Each of the semiconductor structures...
US-1,024,2967 Die encapsulation in oxide bonded wafer stack
Structures and methods of fabricating semiconductor wafer assemblies that encapsulate one or die in a cavity etched into an oxide bonded semiconductor wafer...
US-1,024,2966 Thin bonded interposer package
Methods and systems for a thin bonded interposer package are disclosed and may, for example, include bonding a semiconductor die to a first surface of a...
US-1,024,2965 Semiconductor device including interconnected package on package
A semiconductor device is disclosed including at least first and second vertically stacked and interconnected semiconductor packages. Signal communication...
US-1,024,2964 Wiring substrate for stackable semiconductor assembly and stackable semiconductor assembly using the same
The wiring substrate includes a cavity and a plurality of vertical connecting channels disposed around the cavity. The vertical connecting channels are bonded...
US-1,024,2963 Sensor and manufacturing method thereof
Provided is a manufacturing method of a sensor including the following steps. A mold having a cavity is provided. At least one chip is disposed in the cavity....
US-1,024,2962 Back side metallization
An integrated circuit device wafer includes a silicon wafer substrate and a back side metallization structure. The back side metallization structure includes a...
US-1,024,2961 Semiconductor device
A semiconductor device includes: an insulating substrate including an insulating plate and a circuit board on the insulating plate; a semiconductor chip having...
US-1,024,2960 Integrated passive device for RF power amplifier package
The present disclosure relates to a radio frequency (RF) power transistor package. It further relates to a mobile telecommunications base station comprising...
US-1,024,2958 High-voltage light emitting diode and fabrication method thereof
A fabrication method of a high-voltage light-emitting diode includes the steps of providing a substrate, and forming a light-emitting epitaxial laminated layer...
US-1,024,2957 Compartment shielding in flip-chip (FC) module
Ground shielding is achieved by a conductor shield having conductive surfaces that immediately surround individual chips within a multichip module or device,...
US-1,024,2956 Semiconductor device with metal dam and fabricating method
A semiconductor device is disclosed that may include a first semiconductor die comprising a copper pillar, a second semiconductor die comprising a copper...
US-1,024,2955 Active tamper detection circuit with bypass detection and method therefor
An active tamper detection circuit with bypass detection is provided. A bypass detection circuit is coupled to an active mesh loop. The bypass detector includes...
US-1,024,2954 Electronic circuit package having high composite shielding effect
Disclosed herein is an electronic circuit package includes: a substrate having a power supply pattern; an electronic component mounted on a surface of the...
US-1,024,2953 Semiconductor package with plated metal shielding and a method thereof
Embodiments of the present invention relate to a semiconductor package with a metal-plated shield. Surfaces of molding compound are roughened by an abrasion...
US-1,024,2952 Registration mark formation during sidewall image transfer process
Methods of forming a registration mark may include forming a plurality of mandrels over a hard mask over a semiconductor layer, each mandrel including a spacer...
US-1,024,2951 Optical electronic-chip identification writer using dummy C4 bumps
Embodiments of the invention are directed to a method and resulting structures for forming optically readable chip identification (CID) codes using dummy...
US-1,024,2950 Semiconductor device, method of manufacturing the same and generation method of unique information
A semiconductor device with improved generation function of unique information is provided. The semiconductor device includes an integrated circuit designed or...
US-1,024,2949 Arrangement for spatially limiting a reservoir for a marker material
An arrangement includes a confining layer, a metallization layer and a semiconductor component, wherein the metallization layer is arranged on the semiconductor...
US-1,024,2948 Semiconductor device and method of using substrate having base and conductive posts to form vertical...
A semiconductor device has a substrate including a base and a plurality of conductive posts extending from the base. The substrate can be a wafer-shape, panel,...
US-1,024,2947 SOI wafers with buried dielectric layers to prevent CU diffusion
An SOI semiconductor device includes a first wafer having an active semiconductor layer and a first oxide layer and a second wafer having a semiconductor...
US-1,024,2946 Circuit design having aligned power staples
A multi-layer integrated circuit structure includes (among other components) a first layer having gate conductors, a second layer having M0 conductors, a third...
US-1,024,2945 Backside semiconductor die trimming
A semiconductor die including a substrate, a device layer over the substrate, and an adjustable component in the device layer is provided, where a surface of...
US-1,024,2944 Integrated circuit comprising an antifuse structure and method of realizing
An integrated circuit includes a substrate; an interconnect portion disposed over the substrate, the interconnect portion comprising multiple metallization...
US-1,024,2943 Forming a stacked capacitor
Stacked capacitor structures using TSVs are provided. In one aspect, a stacked capacitor structure includes: a first substrate having at least one first...
US-1,024,2942 Integrated circuit package substrate
Embodiments of the present disclosure are directed towards techniques and configurations for designing and assembling a die capable of being adapted to a number...
US-1,024,2941 Apparatus, system, and method for mitigating warpage of lidless integrated circuits during reflow processes
The disclosed apparatus may include (1) a stiffening brace that (A) is coupled to a top surface of a lidless integrated circuit and (B) includes at least one...
US-1,024,2940 Fan-out ball grid array package structure and process for manufacturing the same
A surface mount structure comprises a redistribution structure, an electrical connection and an encapsulant. The redistribution structure has a first surface...
US-1,024,2939 Semiconductor device and metering apparatus
A semiconductor device includes: an oscillator; a semiconductor chip that includes an oscillation circuit connected to the oscillator, a timer circuit that...
US-1,024,2938 Integrated shunt in circuit package
The disclosure is directed to a circuit on a substrate, such as a leadframe package, that includes shunt to measure current. The shunt is an arched conductor...
US-1,024,2937 Electronic device and method for manufacturing electronic device
To increase a current that can be supplied to an electronic element mounted on an upper surface of a semiconductor package. An electronic device includes a...
US-1,024,2936 Semiconductor device and method of fabricating the semiconductor device
A disclosed semiconductor device includes a buffer layer formed of a compound semiconductor on a substrate, a first semiconductor layer formed of a compound...
US-1,024,2935 Packaged semiconductor device and method for forming
A packaged semiconductor device includes a die attached to a die flag of a lead frame wherein the die includes a first, second, third, and fourth minor side,...
US-1,024,2934 Semiconductor package with full plating on contact side surfaces and methods thereof
Embodiments of the present invention are directed to a semiconductor package with full plating on contact side surfaces. The semiconductor package includes a...
US-1,024,2933 Air gap and air spacer pinch off
Embodiments are directed to a method of forming a semiconductor device and resulting structures having an air spacer between a gate and a contact by forming a...
US-1,024,2932 LDMOS transistor and method
In an embodiment, a semiconductor device includes a semiconductor substrate having a front surface, a LDMOS transistor arranged in the front surface of the...
US-1,024,2931 Liquid cooled compliant heat sink and related method
A heat sink and method for using the same for use in cooling an integrated circuit (IC) chip is provided herein. The heat sink includes a manifold block, a...
US-1,024,2930 Molded resin-sealed power semiconductor device
Freedom of layout is increased, and a small, low-priced molded resin-sealed power semiconductor device is obtained. A molded resin-sealed power semiconductor...
US-1,024,2929 Method of forming a multilayer structure for reducing defects in semiconductor devices and structure
A method of forming a semiconductor device includes providing a semiconductor substrate and forming amorphous semiconductor layers adjacent a major surface of...
US-1,024,2928 Semiconductor device
A semiconductor device includes: a semiconductor substrate having a main plane; a semiconductor element provided on the main plane of the semiconductor...
US-1,024,2927 Semiconductor package, semiconductor device using the same and manufacturing method thereof
A semiconductor package includes a substrate, a first electronic component, a film and a package body. The first electronic component is disposed on the...
US-1,024,2926 Wafer level chip scale package structure and manufacturing method thereof
A wafer level chip scale package (WLCSP) structure and a manufacturing method are disclosed. The WLCSP structure comprises a semiconductor die and a stack. The...
US-1,024,2925 Encapsulation of electronic components in polymer materials
The invention relates to an electronic component (1) comprising at least one semiconductor chip (4) and at least one substrate (6), the semiconductor chip (4)...
US-1,024,2924 Base-attached encapsulant for semiconductor encapsulation, semiconductor apparatus
A base-attached encapsulant for semiconductor encapsulation is used for collectively encapsulating a device-mounted surface of the semiconductor device-mounted...
US-1,024,2923 Formulations containing mixed resin systems and the use thereof for wafer-level underfill for 3D TSV packages
Provided herein are mixed resin systems and the use thereof for wafer-level underfill (WAUF) for three-dimensional TSV packages. In one aspect, there are...
US-1,024,2922 Circuit and method for internally assessing dielectric reliability of a semiconductor technology
A semiconductor wafer includes dielectric regions of different thicknesses, some of the dielectric regions being thinner and other ones of the dielectric...
US-1,024,2921 Method of forming pattern of semiconductor device from which various types of pattern defects are removed
The method includes classifying sample pattern data into a standard normal group and a standard weak group based on a first criterion. The method further...
US-1,024,2920 Integrating and isolating NFET and PFET nanosheet transistors on a substrate
Embodiments of the invention are directed to a method of forming an insulation region during fabrication of a nanosheet channel field effect transistor (FET)....
US-1,024,2919 Vertical transport fin field effect transistors having different channel lengths
A method of forming multiple vertical transport fin field effect transistors (VT FinFETs) having different channel lengths, including, forming a vertical fin on...
← Previous | 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 | Next →

File A Patent Application

  • Protect your idea -- Don't let someone else file first. Learn more.

  • 3 Easy Steps -- Complete Form, application Review, and File. See our process.

  • Attorney Review -- Have your application reviewed by a Patent Attorney. See what's included.