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Patent # Description
US-1,024,2918 Shallow trench isolation structures and contact patterning
A dual layer shallow isolation trench region for semiconductor structures including field effect transistors (FETs) and methods for making the same. The first...
US-1,024,2917 Semiconductor devices including active fins and methods of manufacturing the same
Semiconductor devices may include a plurality of active fins each extending in a first direction on a substrate, a gate structure extending on the active fins...
US-1,024,2916 Stress memorization technique for strain coupling enhancement in bulk FINFET device
A method for forming strained fins includes etching trenches in a bulk substrate to form fins, filling the trenches with a dielectric fill and recessing the...
US-1,024,2915 Method for transferring at least one thin film
A method for transferring at least one thin film from a first substrate to a second substrate is provided, the thin film having a first side and an opposing...
US-1,024,2914 Element chip manufacturing method
A semiconductor chip manufacturing method includes forming a mask on a surface of a semiconductor wafer, forming an opening on the mask, exposing a dividing...
US-1,024,2913 Method of processing a wafer and wafer processing system
A method of processing a wafer having a plurality of devices partitioned by division lines, including attaching the wafer to an adhesive tape supported by a...
US-1,024,2912 Integrated device dies and methods for singulating the same
Integrated device dies and methods for forming one or more of the integrated device dies are disclosed. The integrated device dies can be formed using two step...
US-1,024,2911 Forming self-aligned vias and air-gaps in semiconductor fabrication
A semiconductor device includes a first trench on a mandrel line through a top mask layer and stopping at a middle mask layer; and a second trench on a...
US-1,024,2910 Contact structure and associated method for flash memory
A method for manufacturing a semiconductor device includes providing a substrate structure having an action region and a gate structure having a gate dielectric...
US-1,024,2909 Wet etch removal of Ru selective to other metals
A method for forming a conductive structure for a semiconductor device includes depositing a barrier layer in a trench formed in a dielectric material and...
US-1,024,2908 Airgap formation with damage-free copper
Processing methods may be performed to remove unwanted materials from a substrate, such as an oxide footing. The methods may include forming an inert plasma...
US-1,024,2907 Method for interrupting a line in an interconnect
A method for forming a pattern for an integrated circuit is disclosed. In one aspect, the method includes (a) providing a hardmask layer; (b) overlaying the...
US-1,024,2906 Semiconductor structure with integrated passive structures
A metal-oxide-semiconductor field-effect transistor (MOSFET) with integrated passive structures and methods of manufacturing the same is disclosed. The method...
US-1,024,2905 Wafer pin chuck fabrication and repair
In a wafer chuck design featuring pins or "mesas" making up the support surface, engineering the pins to have an annular shape, or to contain holes or pits,...
US-1,024,2904 Transfer apparatus, processing apparatus, and transfer method
A frame unit is transferred from a cassette to a predetermined position. The frame unit has a platelike workpiece, a tape attached to the workpiece, and a ring...
US-1,024,2903 Suction device, carry-in method, carrier system and exposure apparatus, and device manufacturing method
In a carrier system, a chuck unit is used to hold a placed wafer from above, and vertical-motion pins use suction to hold the wafer from below. Then, the chuck...
US-1,024,2902 Wafer processing laminate, temporary adhesive material for wafer processing, and method for manufacturing thin...
A temporary adhesive material for a wafer processing, used for temporarily bonding a support and a wafer having a circuit-forming front surface and a back...
US-1,024,2901 Systems and methods for wafer alignment
Various embodiments of aligning wafers are described herein. In one embodiment, a photolithography system aligns a wafer by averaging individual via locations....
US-1,024,2900 Storage facility for semiconductor containers
A storage facility for semiconductor containers is provided. The storage structure has partitioning walls including a side wall portion extending along a...
US-1,024,2899 Wafer cassette
A wafer cassette for storing wafers comprises a case and a plurality of carriers for carrying the wafers. Each of the carriers is pivotally and movably mounted...
US-1,024,2898 Article transport facility and inspection unit
An article transport facility includes an alignment portion that aligns the position of an inspection unit that is transferred to a transport target location...
US-1,024,2897 Micro-environment container for photovoltaic cells
Devices and methods for transferring solar cells while maintaining a controlled environment are provided. Such devices can include a solar cell carrying pod...
US-1,024,2896 Substrate storage container
To provide a substrate storage container capable of keeping low a relative humidity in an internal closed space for a long period of time even after purging, a...
US-1,024,2895 Self-contained metrology wafer carrier systems
A self-contained metrology wafer carrier systems and methods of measuring one or more characteristics of semiconductor wafers are provided. A wafer carrier...
US-1,024,2894 Substrate breakage detection in a thermal processing system
Apparatus, systems, and processes for substrate breakage detection in a thermal processing system are provided. In one example implementation, a process can...
US-1,024,2893 Method and apparatus for de-chucking a workpiece using a swing voltage sequence
A method and apparatus for de-chucking a workpiece is described that uses a swing voltage sequence. One example pertains to a method that includes applying a...
US-1,024,2892 Micro pick and bond assembly
Micro pick-and-bond heads, assembly methods, and device assemblies. In, embodiments, micro pick-and-bond heads transfer micro device elements, such as (micro)...
US-1,024,2891 Apparatus and method for securing components of an integrated circuit
Systems and methods of securing an integrated circuit assembly includes: arranging a plurality of securing elements within a plurality of orifices fabricated...
US-1,024,2890 Substrate support with heater
Embodiments of substrate supports with a heater are provided herein. In some embodiments, a substrate support may include a first member to distribute heat to a...
US-1,024,2889 Substrate liquid processing method and substrate liquid processing apparatus
Disclosed is a substrate liquid processing method. The method includes producing a processing liquid including deionized water, carbon dioxide, and ammonia,...
US-1,024,2888 Semiconductor processing apparatus with a ceramic-comprising surface which exhibits fracture toughness and...
A solid solution-comprising ceramic article useful in semiconductor processing, which article may be in the form of a solid, bulk ceramic, or may be in the form...
US-1,024,2887 Semiconductor device and method of making embedded wafer level chip scale packages
A semiconductor device includes a carrier and a plurality of semiconductor die disposed over the carrier. An encapsulant is deposited over the semiconductor...
US-1,024,2886 Method for fabricating array substrate
A method for fabricating an array substrate is disclosed. The method comprises: forming a first oxide semiconductor active layer of a first TFT in a GOA area of...
US-1,024,2884 Integration of air-sensitive two-dimensional materials on arbitrary substrates for the manufacturing of...
A field-effect transistor and method for fabricating such a field-effect transistor that utilizes an air-sensitive two-dimensional material (e.g., silicene). A...
US-1,024,2883 High aspect ratio etch of oxide metal oxide metal stack
A method for etching features in an OMOM stack with first layer of silicon oxide, a second layer of a metal containing material over the first layer, a third...
US-1,024,2882 Cyclic etch process to remove dummy gate oxide layer for fin field effect transistor fabrication
Methods are provided to implement a cyclic etch process to remove oxide layers for semiconductor device fabrication. For example, a method comprises performing...
US-1,024,2881 Self-aligned single dummy fin cut with tight pitch
A method of forming a semiconductor device and resulting structures having a dummy semiconductor fin removed from within an array of tight pitch semiconductor...
US-1,024,2880 Method of wet etching and method of fabricating semiconductor device using the same
Disclosed are a method of wet etching and a method of fabricating a semiconductor device. The wet etching method includes providing a wafer in a process bath...
US-1,024,2879 Methods and apparatus for forming smooth and conformal cobalt film by atomic layer deposition
Provided herein are atomic layer deposition (ALD) methods of depositing cobalt in a feature. The methods involve two-step surface treatments during an ALD...
US-1,024,2878 Substrate processing method and recording medium
A substrate processing method is for forming a metal film on a target substrate by using a plasma. The method includes loading a target substrate having a...
US-1,024,2877 Aluminum compound and methods of forming thin film and fabricating integrated circuit device by using the same
Provided are an aluminum compound represented by General Formula (I), a method of forming a thin film, and a method of fabricating an integrated circuit device....
US-1,024,2876 Method for manufacturing semiconductor device
Provided is a method including the following steps: forming an insulating film having a thickness of 0.5 .mu.m or greater on an epitaxial layer provided with a...
US-1,024,2875 Impurity diffusion agent composition and method for manufacturing semiconductor substrate
A diffusion agent composition that, even when a semiconductor substrate which is an object into which an impurity diffusion ingredient is to be diffused has, on...
US-1,024,2874 Diffusing agent composition and method of manufacturing semiconductor substrate
A diffusing agent composition and a method of manufacturing a semiconductor substrate using the diffusing agent composition. The diffusing agent composition...
US-1,024,2873 RF power compensation to control film stress, density, resistivity, and/or uniformity through target life
Methods for depositing a metal-containing layer atop a substrate disposed in a PVD chamber are provided herein. In some embodiments, such a method includes:...
US-1,024,2872 Rework of patterned dielectric and metal hardmask films
A method for reworking a semiconductor device includes, in a pattern stack formed on an interlevel dielectric (ILD) layer, polishing the pattern stack to remove...
US-1,024,2871 Resist underlayer film-forming composition including a compound having an amino group protected with a...
There is provided a composition that a resist pattern having a reduced LWR representing variations in line width of the resist pattern, compared to conventional...
US-1,024,2870 Method for producing patterns
A method for producing patterns in a layer to be etched, from a stack including at least the layer to be etched and a masking layer overlying the layer to be...
US-1,024,2869 Method of manufacturing switching element having gallium nitride substrate
A method of manufacturing a switching element includes forming a recessed portion in a surface of a GaN semiconductor substrate in which a first n-type...
US-1,024,2868 Seed crystal for growth of gallium nitride bulk crystal in supercritical ammonia and fabrication method
In one instance, the seed crystal of this invention provides a nitrogen-polar c-plane surface of a GaN layer supported by a metallic plate. The coefficient of...
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