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Patent # Description
US-1,024,2766 Highly bendable insulated electric wire and wire harness
A highly bendable insulated electric wire includes a conductor part that has a plurality of non-compressed strands made of a copper alloy, each of the...
US-1,024,2765 Conductive member, image forming apparatus, conductive particle and method for manufacturing the same
Conductive particle 10 has conductive carbon black particle (CB) 11 and cover layer 12. The amount of an insulating resin in conductive particle 10 is from 10...
US-1,024,2764 Internal electrode paste
An internal electrode paste including Ag as a conductor, a resin, and a solvent. Wherein the resin is of a type where 100% of the resin burns in a temperature...
US-1,024,2763 Joined body, honeycomb structure, method for producing joined body, and covered body
A joined body 20 includes a first member 22 having a thermal expansion coefficient of 8 ppm/K or less, a second member 24 having a thermal expansion coefficient...
US-1,024,2762 Copper alloy wire rod and method for manufacturing copper alloy wire rod
A copper alloy wire rod containing Ag: 0.5 wt % or more and 6 wt % or less and the balance including inevitable impurities and Cu, in which, on a cross section...
US-1,024,2761 Method for preparation of alpha sources of polonium using sulfide micro-precipitation
A method for preparing alpha sources of polonium. A sample of polonium is provided in a solution. A controlled amount of sulfide and a controlled amount of a...
US-1,024,2760 System and method for generating molybdenum-99 and metastable technetium-99, and other isotopes
Accelerator based systems are disclosed for the generation of isotopes, such as molybdenum-98 ("99Mo") and metastable technetium-99 ("99mTc") from molybdenum-98...
US-1,024,2759 Control rod drive mechanism
A control rod drive mechanism includes an outer tube and a guide tube which is arranged in the outer tube and is held by the outer tube. Furthermore, the...
US-1,024,2758 Method of operating a pressurized-water nuclear reactor allowing same to pass from a plutonium equilibrium...
A method is provided for operating a nuclear reactor. The method includes operating the nuclear reactor for at least one plutonium equilibrium cycle during...
US-1,024,2757 Predictive wellness management
Socially aware guidance and differential access controls within a control zone are determined for users based on individual wellness goals and predicted...
US-1,024,2756 Systems and methods for predicting metabolic and bariatric surgery outcomes
Various systems and methods for predicting metabolic and bariatric surgery outcomes are provided. The systems and methods can also provide predictions for...
US-1,024,2755 Systems and methods for translating messages between a healthcare entity and a vendor entity
An inbound message including medical record content may be received. The inbound message may indicate a healthcare entity and a vendor entity. It may be...
US-1,024,2754 Method for providing therapy to an individual
A method and system for providing therapy to an individual, the method comprising: transmitting a log of use dataset associated with communication behavior of...
US-1,024,2753 Method for measuring strength of associations of multidimensional traits
A method of measuring a subject's strength of associations of multidimensional traits involving each of a first pair of first and second categories with each of...
US-1,024,2752 Method for screening bad column and data storage device with bad column summary table
A method for screening bad columns applicable to a data storage medium is disclosed. The method for screening bad columns includes steps of: reading out written...
US-1,024,2751 Method and apparatus for providing preloaded non-volatile memory content
An embodiment providing one or more improvements includes a memory loading system and method for at least managing testing of a memory unit using a memory test...
US-1,024,2750 High-speed data path testing techniques for non-volatile memory
Techniques are presented for testing the high-speed data path between the IO pads and the read/write buffer of a memory circuit without the use of an external...
US-1,024,2749 Calibration apparatus and method for sampler with adjustable high frequency gain
Methods and systems are described for receiving a sampling signal, pre-charging a pair of output nodes prior to a sampling interval, initiating the sampling...
US-1,024,2748 Voltage generation circuit which is capable of executing high-speed boost operation
According to one embodiment, a voltage generation circuit includes a first boost circuit, a voltage division circuit, a first detection circuit, a capacitor and...
US-1,024,2747 Charge loss failure mitigation
Methods of operating a memory include reading a particular grouping of memory cells using a read voltage having a particular voltage level, determining a number...
US-1,024,2746 Shielded vertically stacked data line architecture for memory
Apparatuses and methods are disclosed, including an apparatus that includes first and second strings of vertically stacked memory cells, and first and second...
US-1,024,2745 Semiconductor memory device that generates voltages applied to memory cells based on a signal from a...
A semiconductor memory device includes a memory cell array, a temperature sensor that generates a first voltage which is based on a temperature of the...
US-1,024,2744 Boosting channels of memory cells
A method for programming a non-volatile memory device includes concurrently boosting channels of memory cells in a selected memory string and an unselected...
US-1,024,2743 Method and apparatus for writing nonvolatile memory using multiple-page programming
A method of storing information or data in a nonvolatile memory device with multiple-page programming. The method, in one aspect, is able to activate a first...
US-1,024,2742 Segmented memory and operation
Apparatus having a plurality of strings of series-connected memory cells, and methods of their operation, where each string of the plurality of strings is...
US-1,024,2741 Low voltage difference operated EEPROM and operating method thereof
The present invention discloses a low voltage difference-operated EEPROM and an operating method thereof wherein at least one transistor structure is formed in...
US-1,024,2740 T-CAM bier bit-string lookups
In one embodiment of a system, apparatus, and method the system, apparatus, and method including a table of neighboring network nodes stored in a ternary...
US-1,024,2739 Memory cells, memory cell arrays, methods of using and methods of making
A semiconductor memory cell and arrays of memory cells are provided In at least one embodiment, a memory cell includes a substrate having a top surface, the...
US-1,024,2738 Resistance variable element methods and apparatuses
Apparatus and methods are disclosed, including a method that performs a first operation on a first resistance variable element using a common source voltage, a...
US-1,024,2737 Device structure for neuromorphic computing system
An array of resistance cells has a number M of rows and a number N of columns of resistance cells. Each cell comprises a transistor having a threshold,...
US-1,024,2736 Reference currents for input current comparisons
An example device includes a first module, a second module, and a third module. The first module is to compare an input current to a first reference current,...
US-1,024,2735 Nonvolatile semiconductor memory device
A nonvolatile semiconductor memory device comprises a cell array including a plurality of first lines, a plurality of second lines intersecting the plurality of...
US-1,024,2734 Resuming storage die programming after power loss
Provided are techniques for resuming storage die programming after power loss. In response to receipt of an indication of the power loss, data that was to be...
US-1,024,2733 Semiconductor memory device that can stably perform writing and reading without increasing current consumption...
Cell power supply lines are arranged for memory cell columns, and adjust impedances or voltage levels of the cell power supply lines according to the voltage...
US-1,024,2732 Memory elements with soft-error-upset (SEU) immunity using parasitic components
An integrated circuit is provided that includes memory elements that exhibit immunity to soft error upset (SEU) events when subjected to high-energy atomic...
US-1,024,2731 Memory device for controlling refresh operation by using cell characteristic flags
A memory device includes a memory cell array that includes a plurality of memory cell rows; and a refresh address generator configured to store flags...
US-1,024,2730 Double data rate (DDR) memory controller apparatus and method
In accordance with one embodiment, an apparatus is provided, comprising: a double data rate (DDR) memory controller that, when in operation, causes the...
US-1,024,2729 Semiconductor device suppressing BTI deterioration
Disclosed herein is a device includes a command generation circuit: that activates first and second command signals, an internal circuit that includes a...
US-1,024,2728 DPU architecture
A dynamic random access memory (DRAM) processing unit (DPU) may include at least one computing cell array having a plurality of DRAM-based computing cells...
US-1,024,2727 Reduction of power consumption in memory devices during refresh modes
Devices, systems, and methods include an active mode to accommodate read/write operations of a memory device and a self-refresh mode to accommodate recharging...
US-1,024,2726 Memory arrays, and methods of forming memory arrays
Some embodiments include an assembly having active material structures arranged in an array having rows and columns. Each of the active material structures has...
US-1,024,2725 Modular magnetoresistive memory
Apparatus and method contemplating a magnetoresistive memory apparatus having a read element having a high resistance material selected to optimize read...
US-1,024,2724 Apparatuses and methods for voltage level control
Apparatuses for voltage level control in a semiconductor device are described. An example apparatus includes: a plurality of circuits coupled in parallel...
US-1,024,2723 Method and apparatus for background memory subsystem calibration
A method and apparatus for performing a background calibration in a memory subsystem is disclosed. A memory subsystem includes a memory controller coupled to a...
US-1,024,2722 Shifting data in sensing circuitry
The present disclosure includes apparatuses and methods related to shifting data. An example apparatus comprises sensing circuitry including a sense amplifier...
US-1,024,2721 Shifting data in sensing circuitry
The present disclosure is related to shifting data using sensing circuitry. An example apparatus can include a first sensing component and a second sensing...
US-1,024,2720 Dual sensing current latched sense amplifier
A sense amplifier and method thereof are provided. The sense amplifier includes first and second transistors coupled to first and second bit lines,...
US-1,024,2719 Power management of a memory device by dynamically changing supply voltage
An electronic device includes a memory device including a power switch configured to provide one of a first voltage and a second voltage to an internal circuit...
US-1,024,2718 Flexible memory system with a controller and a stack of memory
Embodiments of a system and method for providing a flexible memory system are generally described herein. In some embodiments, a substrate is provided, wherein...
US-1,024,2717 Extended platform with additional memory module slots per CPU socket
Electronic devices and methods including a printed circuit board configured to accept CPUs and memory modules are described. One apparatus includes a printed...
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