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Patent # Description
US-1,024,1952 Throttling integrated link
Methods and apparatus for throttling an interface that is integrated on the same die as a processor are described. In one embodiment, a signal from an...
US-1,024,1951 Device full memory access through standard PCI express bus
A method of transferring data between a host and a PCI device is disclosed. The method comprises mapping a fixed memory-mapping control block in a host memory...
US-1,024,1950 Multipath I/O proxy device-specific module
A method, non-transitory machine readable medium, and system are provided for modifying a device-specific module (DSM) corresponding to a storage device. In...
US-1,024,1949 Transmission device, DP source device, reception device, and DP sink device
A transmission device includes a converter and a transmitter. The converter converts a plurality of link symbols in DisplayPort (DP) into a data block in Gen 2...
US-1,024,1948 Differential amplitude detector
An example embodiment includes an idle state detection circuit. The idle state detection circuit includes a bias current loop, a rectifying circuit loop, a...
US-1,024,1947 Hardware-based virtual machine communication
A processing system includes a processor and a VM-to-VM communication accelerator circuit comprising a first interface device to support direct memory access...
US-1,024,1946 Multi-channel DMA system with command queue structure supporting three DMA modes
A method, system, and apparatus are provided for managing multiple DMA channels in different DMA modes by processing command sequences associated with different...
US-1,024,1945 Memory move supporting speculative acquisition of source and destination data granules including copy-type and...
In a data processing system implementing a weak memory model, a lower level cache receives, from a processor core, a plurality of copy-type requests and a...
US-1,024,1944 Packet processing efficiency based interrupt rate determination
Interrupt rate determination can include instructions to determine a quantity of instances of packet processing by an operating system during a first period of...
US-1,024,1943 Memory channel that supports near memory and far memory access
A semiconductor chip comprising memory controller circuitry having interface circuitry to couple to a memory channel. The memory controller includes first logic...
US-1,024,1942 Method and apparatus for memory access
Aspects of the disclosure provide an integrated circuit (IC) chip that includes interface circuits and a control circuit. The interface circuits is configured...
US-1,024,1941 Systems and methods for asymmetric memory access to memory banks within integrated circuit systems
Methods and systems are disclosed for asymmetric memory access to memory banks within integrated circuit (IC) systems. Disclosed embodiments include a memory...
US-1,024,1940 Memory module with reduced read/write turnaround overhead
A memory module includes a substrate, plural memory devices, and a buffer. The plural memory devices are organized into at least one rank, each memory device...
US-1,024,1938 Output data path for non-volatile memory
Apparatuses, systems, and methods are disclosed for an output data path for non-volatile memory. A buffer may include a plurality of buffer stages. A buffer...
US-1,024,1937 Adjusting an optimization parameter to customize a signal eye for a target chip on a shared bus
The embodiments of the present disclosure identify a target chip from among multiple chips coupled to a shared bus and customize an optimization parameter for...
US-1,024,1936 Method for actively connecting to and communicating with apple device and apple device attachment
A method for actively initiating a connection to and communicating with an Apple device via USB, relating to the field of communications, and comprising: an...
US-1,024,1935 Portable device, cable assembly, and USB system
One aspect includes a system, including: a portable device having a receptacle; and a cable assembly including a plug connectable to the receptacle; the cable...
US-1,024,1934 Shared memory controller, shared memory module, and memory sharing system
According to an embodiment, upon receiving a use request including an identifier of a program and authentication information, a use request processing unit...
US-1,024,1933 Support apparatus and method for processing data and using hardware support for atomic memory transactions
An asymmetric multiprocessor system includes a plurality of processor cores supporting transactional memory via controllers as well as one or more processor...
US-1,024,1932 Power saving method and apparatus for first in first out (FIFO) memories
In various embodiments, apparatuses and methods are disclosed to keep a memory clock gated when the data for a current memory address is the same as the data in...
US-1,024,1931 Controlling access to pages in a memory in a computing device
A table walker receives, from a requesting entity, a request to translate a first address into a second address associated with a page of memory. During a...
US-1,024,1930 Storing data in a server computer with deployable encryption/decryption infrastructure
For storing data in a data-storage structure of a server computer, an infrastructure is deployed to a server computer. The infrastructure has a forwarder module...
US-1,024,1929 Data transfer method for parallel transfer of data divided into a plurality of data groups over multiple TCP...
A processor transfers a file in a memory by TCP (Transmission Control Protocol). The processor divides single file in the memory into the data group of the N...
US-1,024,1928 Maintaining cache consistency in a cache for cache eviction policies supporting dependencies
For maintaining consistency for a cache that contains dependent objects in a computing environment, object dependencies for cached objects are managed by...
US-1,024,1927 Linked-list-based method and device for application caching management
A linked-list-based method for application caching management is disclosed, the method including: when receiving application cached data, creating a node in a...
US-1,024,1926 Migrating buffer for direct memory access in a computer system
A computer-implemented method for migrating a buffer used for direct memory access (DMA) may include receiving a request to perform a DMA data transfer between...
US-1,024,1925 Selecting a default page size in a variable page size TLB
Systems, apparatuses, and methods for selecting default page sizes in a variable page size translation lookaside buffer (TLB) are disclosed. In one embodiment,...
US-1,024,1924 Reducing over-purging of structures associated with address translation using an array of tags
A marking capability is used to provide an indication of whether a block of memory is being used by a guest control program to back an address translation...
US-1,024,1923 Configurable I/O address translation data structure
In response to a determination to allocate additional storage, within a real address space employed by a system memory of a data processing system, for...
US-1,024,1922 Processor and method
Provided is a processor including a plurality of devices. The processor includes a source processing device configured to identify data to request from another...
US-1,024,1921 Avoid cache lookup for cold cache
Methods and apparatus relating to techniques for avoiding cache lookup for cold cache. In an example, an apparatus comprises logic, at least partially...
US-1,024,1920 Systems and methods for coordinating interdependent asynchronous reads
Implementations described and claimed herein provide a coordination of interdependent asynchronous reads. In one implementation, an input/output request for a...
US-1,024,1919 Data caching method and computer system
A data caching method and a computer system are provided. In the method, when a miss of an access request occurs and a cache needs to determine a to-be-replaced...
US-1,024,1918 Considering a frequency of access to groups of tracks to select groups of tracks to destage
Provided are a computer program product, system, and method for considering a frequency of access to groups of tracks to select groups of tracks to destage. A...
US-1,024,1917 Identification of a computing device accessing a shared memory
A method for identifying, in a system including two or more computing devices that are able to communicate with each other, with each computing device having...
US-1,024,1916 Sparse superline removal
Provided are an apparatus, system, and method for sparse superline removal. In response to occupancy of a replacement tracker (RT) exceeding an RT eviction...
US-1,024,1913 Operating local caches for a shared storage device
Aspects include creating a network multicast group in a storage area network (SAN) for a first computer system and a second computer system that are connected...
US-1,024,1912 Apparatus and method for implementing a multi-level memory hierarchy
A system and method are described for integrating a memory and storage hierarchy including a non-volatile memory tier within a computer system. In one...
US-1,024,1911 Modification of multiple lines of cache chunk before invalidation of lines
Examples described herein relate to caching in a system with multiple nodes sharing a globally addressable memory. The globally addressable memory includes...
US-1,024,1910 Creating a dynamic address translation with translation exception qualifiers
An enhanced dynamic address translation facility product is created such that, in one embodiment, a virtual address to be translated and an initial origin...
US-1,024,1909 Non-volatile memory device
A write frequency of a non-volatile memory is determined at a fine granularity while suppressing consumption of the volatile memory. When it is determined that...
US-1,024,1908 Techniques for dynamically determining allocations and providing variable over-provisioning for non-volatile...
Dynamically varying Over-Provisioning (OP) enables improvements in lifetime, reliability, and/or performance of a Solid-State Disk (SSD) and/or a flash memory...
US-1,024,1907 DBMS storage management for non-volatile memory
A system includes reception of an instruction to create a data block associated with a portion of a database table in a non-volatile memory system, creation, in...
US-1,024,1906 Memory subsystem to augment physical memory of a computing system
Systems and methods are provided for implementing a memory subsystem to augment physical memory of a computing system. For example, a system comprises a memory...
US-1,024,1905 Managing an effective address table in a multi-slice processor
Methods and apparatus for managing an effective address table (EAT) in a multi-slice processor including receiving, from an instruction sequence unit, a...
US-1,024,1904 Test components factorization in a build system
The factorization of test components when performing component-level regression testing in iterative builds of a computing system that consists of many working...
US-1,024,1903 Parallel testing and reporting system
An optimized test data selection strategy references a sampling file that identifies data attributes that serve as the basis of the test data selection...
US-1,024,1902 Systems and methods for benchmark based cross platform service demand prediction
Systems and methods for benchmark based cross platform service demand prediction includes generation of performance mimicking benchmarks that require only...
US-1,024,1901 Web application performance testing
A system for performance testing a web application initializes to be instrumented a subset of methods of the web application to be tested in response to a...
US-1,024,1900 Data records selection
A computer-implemented method includes accessing a plurality of data records, each data record having a plurality of data fields. The method further includes...
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