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Patent # Description
US-1,024,9777 Infrared light emitting diode
An infrared light-emitting diode includes, from up to bottom, a P-type ohmic electrode, a contact layer, a P-type cladding layer, an active layer, an N-type...
US-1,024,9776 Heterojunction solar cell and manufacturing method thereof
Discussed is a method of manufacturing a heterojunction solar cell, including: forming a metal compound on a semiconductor substrate; forming a transparent...
US-1,024,9775 Solar cell and method for producing solar cell
A solar cell includes: first and second conductivity type diffusion layers which are formed on a backside of a light-receiving surface of a substrate, first and...
US-1,024,9774 Conductive paste for forming solar cell electrode
A conductive paste for forming solar cell electrodes that obtains favorable electrical characteristics and sufficient adhesion strength to a substrate. The...
US-1,024,9773 Light emitting diode and fabrication method thereof
A light-emitting diode chip includes a first semiconductor layer, a second semiconductor layer and an active layer between them; an dielectric layer having a...
US-1,024,9772 Solar cell
A solar cell having an electrical modulating stack layer is provided. The solar cell includes a first electrode, a second electrode, a photoelectric conversion...
US-1,024,9771 Filter collimators and methods for forming the same
A filter collimator is provided. The filter collimator includes a substrate having a photodiode. The filter collimator also includes an interference-type and an...
US-1,024,9770 Solar cell module
The solar cell module according to the present invention includes: a supporting substrate; a back electrode layer arranged on the supporting substrate; a light...
US-1,024,9769 On-chip tuneable diffusion resistor
An object of the disclosure is to take a CMOS varactor structure (NMOS in N-well or PMOS in P-well) and turn it in to a three terminal on-chip tuneable...
US-1,024,9768 Semiconductor device
The semiconductor device includes a first transistor provided in a driver circuit portion and a second transistor provided in a pixel portion; the first...
US-1,024,9767 Ga.sub.2O.sub.3-based semiconductor element
A Ga.sub.2O.sub.3-based semiconductor element includes an undoped .beta.-Ga.sub.2O.sub.3 single crystal film disposed on a surface of a .beta.-Ga.sub.2O.sub.3...
US-1,024,9766 Semiconductor device including a transistor, a wiring and a barrier film
In a semiconductor device including a transistor, an oxygen release type oxide insulating film is formed in contact with a channel formation region of the...
US-1,024,9765 Semiconductor device and electronic device
To provide a highly reliable semiconductor device that is suitable for miniaturization and higher density. A semiconductor device includes a first electrode...
US-1,024,9764 Semiconductor device, display device including semiconductor device, electronic device including semiconductor...
A method for manufacturing a transistor with stable electric characteristics and little signal delay due to wiring resistance, used in a semiconductor device...
US-1,024,9763 Array substrate, and display device, and fabrication methods
A semiconductor device, an array substrate, and a display device, and their fabrication methods are provided. An exemplary semiconductor device includes a first...
US-1,024,9762 Vertically aligned nanowire channels with source/drain interconnects for nanosheet transistors
A nano-sheet semiconductor structure and a method for fabricating the same. The nano-sheet structure includes a substrate and at least one alternating stack of...
US-1,024,9761 Thin-film transistor substrate
A thin-film transistor (TFT) substrate is provided which includes: a substrate; a TFT disposed above the substrate; and a capacitor disposed above the substrate...
US-1,024,9760 Thin film transistor and liquid crystal display panel
The disclosure discloses a thin film transistor and a manufacturing method thereof, a liquid crystal display panel, a transition pattern is disposed between a...
US-1,024,9759 Connection arrangements for integrated lateral diffusion field effect transistors
In an active layer over a semiconductor substrate, a semiconductor device has a first lateral diffusion field effect transistor (LDFET) that includes a source,...
US-1,024,9758 FinFET with sigma recessed source/drain and un-doped buffer layer epitaxy for uniform junction formation
After forming a gate structure over a semiconductor fin that extends upwards from a semiconductor substrate portion, a sigma cavity is formed within the...
US-1,024,9757 Semiconductor device and method of fabricating the same
A substrate includes a pattern forming region and a peripheral region. A first strain relaxed buffer layer is disposed on the pattern forming region of the...
US-1,024,9756 Semiconductor device including memory and logic circuit having FETs with ferroelectric layer and manufacturing...
A semiconductor device includes a memory circuit and a logic circuit. The memory circuit includes a word line, a bit line, a common line and a memory transistor...
US-1,024,9755 Transistor with asymmetric source/drain overlap
An asymmetric field-effect transistor having different gate-to-source and gate-to-drain overlaps allows lower parasitic capacitance on the drain side of the...
US-1,024,9754 Precise junction placement in vertical semiconductor devices using etch stop layers
A semiconductor device is provided that includes a first of a source region and a drain region comprised of a first semiconductor material, wherein an etch stop...
US-1,024,9753 Gate cut on a vertical field effect transistor with a defined-width inorganic mask
A method of cutting a gate on a VFET includes depositing a memorization layer around a spacer on a sidewall of the field effect transistor. A planarizing layer...
US-1,024,9752 Semiconductor devices having segmented ring structures
In one embodiment, the semiconductor devices relate to using one or more super-junction trenches for termination.
US-1,024,9751 High-speed diode with crystal defects and method of manufacturing
A high-speed diode includes an n-type semiconductor layer and a p-type semiconductor layer which is laminated on the n-type semiconductor layer, where a pn...
US-1,024,9750 Semiconductor device
A semiconductor device includes a first semiconductor layer. A second semiconductor layer is disposed on the first semiconductor layer. A structure layer is...
US-1,024,9749 Semiconductor device and method for manufacturing the same
A semiconductor device includes a buffer layer, a channel layer, and a carrier supply layer; first and second recesses formed in the channel layer and the...
US-1,024,9748 Nitride semiconductor device
A nitride semiconductor device includes: a substrate of a first conductivity type having a first surface and a second surface on a side of the substrate...
US-1,024,9747 Turn-off power semiconductor device with improved centering and fixing of a gate ring, and method for...
The present application relates to a turn-off power semiconductor device having a wafer with an active region and a termination region surrounding the active...
US-1,024,9746 Bipolar transistor with superjunction structure
A superjunction bipolar transistor includes an active transistor cell area that includes active transistor cells electrically connected to a first load...
US-1,024,9745 Method for making a semiconductor device including a resonant tunneling diode structure having a superlattice
A method for making a semiconductor device may include forming at least one double-barrier resonant tunneling diode (DBRTD) by forming a first doped...
US-1,024,9744 Tunnel field-effect transistor and method for manufacturing tunnel field-effect transistor
A tunnel field-effect transistor and a method for manufacturing a tunnel field-effect transistor is disclosed. Source regions are located on two sides of an...
US-1,024,9743 Semiconductor device with low band-to-band tunneling
The invention includes a semiconductor device comprising an interlevel dielectric layer over a buried insulator layer over a semiconductor substrate; a source...
US-1,024,9742 Offstate parasitic leakage reduction for tunneling field effect transistors
A method including forming a non-planar conducting channel of a device between junction regions on a substrate, the substrate including a blocking material...
US-1,024,9741 System and method for ion-selective, field effect transistor on flexible substrate
A flexible ion-selective field effect transistor (ISFET) and methods of making the same are disclosed. The methods may comprise: (a) attaching a flexible...
US-1,024,9740 Ge nano wire transistor with GaAs as the sacrificial layer
An apparatus including a three-dimensional semiconductor body including a channel region and junction regions disposed on opposite sides of the channel region,...
US-1,024,9739 Nanosheet MOSFET with partial release and source/drain epitaxy
A method is presented for forming a nanosheet metal oxide semiconductor field effect transistor (MOSFET) structure. The method includes forming a ...
US-1,024,9738 Nanosheet channel-to-source and drain isolation
A method and structures are used to fabricate a nanosheet semiconductor device. Nanosheet fins including nanosheet stacks including alternating silicon (Si)...
US-1,024,9737 Silicon germanium-on-insulator formation by thermal mixing
A layer of amorphous silicon is formed on a germanium-on-insulator substrate, or a layer of germanium is formed on a silicon-on-insulator substrate. An anneal...
US-1,024,9736 Aspect ratio trapping in channel last process
A method of forming the fin structure that includes forming a replacement gate structure on a channel region of the at least one replacement fin structure; and...
US-1,024,9735 Thin film transistor, method for manufacturing the same, array substrate, and display device
The present disclosure provides a TFT, its manufacturing method, an array substrate and a display device. The method includes steps of: forming a pattern of a...
US-1,024,9734 Poly-silicon thin film transistor and manufacturing method thereof, array substrate and manufacturing method...
A poly-silicon thin film transistor and its manufacturing method, an array substrate and its manufacturing method, and a display device are provided. The method...
US-1,024,9733 Transistor and manufacturing method of transistor
Provided are an air up type transistor which has high electrical connection reliability and high productivity, and is capable of exhibiting good transistor...
US-1,024,9732 Manufacturing method of semiconductor device to uniformly form thickness of gate insulating layer
A manufacturing method of a semiconductor device is provided. The method includes sequentially forming an n- type of layer, a p type of region, and an n+ type...
US-1,024,9731 Vertical FET with sharp junctions
VFET devices and techniques for formation thereof having well-defined, sharp source/drain-to-channel junctions are provided. In one aspect, a method of forming...
US-1,024,9730 Controlling gate profile by inter-layer dielectric (ILD) nanolaminates
A semiconductor structure includes a substrate, a plurality of parallel fins extending above the substrate, a plurality of gate structures perpendicular to the...
US-1,024,9729 Method for fabricating metal replacement gate semiconductor device using dummy gate and composite spacer structure
A method for fabricating a semiconductor device. After forming SiGe epitaxial layer within the Core_p region, the hard mask is removed. A contact etch stop...
US-1,024,9728 Air-gap gate sidewall spacer and method
Disclosed are integrated circuit (IC) structures and formation methods. In the methods, a gate with a sacrificial gate cap and a sacrificial gate sidewall...
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