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Patent # Description
US-1,024,9622 Epitaxial oxide fin segments to prevent strained semiconductor fin end relaxation
A method of forming a semiconductor device that includes providing regions of epitaxial oxide material on a substrate of a first lattice dimension, wherein...
US-1,024,9621 Dummy contacts to mitigate plasma charging damage to gate dielectrics
A method of limiting plasma charging damage on ICs. A die includes gate stacks on active areas defined by a field dielectric. A pre-metal dielectric (PMD) layer...
US-1,024,9620 Semiconductor device and power amplifier circuit
A semiconductor device includes a semiconductor substrate and first and second bipolar transistors. The semiconductor substrate includes first and second main...
US-1,024,9619 Power semiconductor device having trench gate type IGBT and diode regions
Switching loss is reduced. A first surface of a semiconductor substrate has a portion included in an IGBT region and a portion included in a diode region....
US-1,024,9618 Power semiconductor device having trench gate type IGBT and diode regions
Switching loss is reduced. A first surface of a semiconductor substrate has a portion included in an IGBT region and a portion included in a diode region....
US-1,024,9617 Tunable device having a FET integrated with a BJT
A device includes a field effect transistor (FET) integrated with at least a portion of a bipolar junction transistor (BJT), in which a back gate of the FET...
US-1,024,9616 Methods of forming a resistor structure between adjacent transistor gates on an integrated circuit product and...
One illustrative method disclosed herein includes, among other things, forming first and second adjacent gates above a semiconductor substrate, each of the...
US-1,024,9615 MISHFET and Schottky device integration
A semiconductor device includes a substrate comprising a heterostructure configured to support formation of a channel during operation, first and second...
US-1,024,9614 Semiconductor device
Provided is a semiconductor device including a gate structure, a first doped region of a first conductivity type, a plurality of second doped regions of a...
US-1,024,9613 Electrostatic discharge device and manufacturing method thereof, array substrate, display panel and device
An electrostatic discharge device comprises a transistor with one of its source and drain serving as an input terminal of said device and the other serving as...
US-1,024,9612 Semiconductor device including self-protecting current sensor
A semiconductor device includes a semiconductor body having a first surface and a second surface opposite to the first surface. The semiconductor body includes...
US-1,024,9611 Diode string configured with guard ring silicon-controlled rectifier for negative electrostatic discharge...
A diode string for a semiconductor circuit configured with a guard ring silicon-controlled rectifier (SCR) for electrostatic discharge (ESD) protection. The...
US-1,024,9610 IGBT coupled to a reverse bias device in series
In some examples, an electrostatic discharge (ESD) device comprises an insulated-gate bipolar transistor (IGBT) comprising a source terminal, an anode terminal,...
US-1,024,9609 Apparatuses for communication systems transceiver interfaces
An integrated circuit device for protecting circuits from transient electrical events is disclosed. An integrated circuit device includes a first bipolar...
US-1,024,9608 ESD protection circuit
An electrostatic protection circuit is disclosed. The electrostatic protection circuit includes delay circuitry coupled between a supply voltage node and a...
US-1,024,9607 Internally stacked NPN with segmented collector
An integrated circuit includes a stacked NPN having an upper NPN connected to a lower NPN. The upper NPN includes an upper collector, an upper base, and an...
US-1,024,9606 Semiconductor device
A semiconductor device includes: a first domain including a first high power source line, a first low power source line, and a first power clamp circuit; a...
US-1,024,9605 Integrated circuit devices
An integrated circuit (IC) device includes at least one standard cell. The at least one standard cell includes: first and second active regions respectively...
US-1,024,9604 Semiconductor device and method of manufacturing the same
A semiconductor device includes a base substrate and a semiconductor chip on the base substrate, the semiconductor chip including a first layer structure and a...
US-1,024,9603 Pixel structure, display device including the pixel structure, and method of manufacturing the pixel structure
A pixel structure, a display device, and a method of manufacturing a pixel structure, the pixel structure including a base substrate; at least one first...
US-1,024,9602 Light emitting diode display and manufacture method thereof
The present invention provides a light emitting diode display and a manufacture method thereof. The manufacture method of the light emitting diode display...
US-1,024,9601 Fan-out semiconductor package module
A fan-out semiconductor package includes a first connection member having a through-hole, a semiconductor chip with connection pads on its active surface...
US-1,024,9600 Light emitting apparatus, illumination apparatus and display apparatus
A light emitting apparatus including: one or a plurality of light emitting devices each having a plurality of electrodes and each emitting light from the upper...
US-1,024,9599 Laminated printed color conversion phosphor sheets
Embodiments are related generally to electronic displays and, more particularly, to emissive displays made with transparent sheets having phosphor dots on the...
US-1,024,9598 Integrated circuit package having wirebonded multi-die stack
Embodiments of the present disclosure are directed towards an integrated circuit (IC) package including a first die at least partially embedded in a first...
US-1,024,9597 Systems, methods, and apparatuses for implementing die recovery in two-level memory (2LM) stacked die subsystems
Systems, methods, and apparatuses for implementing die recovery in Two-Level Memory (2LM) stacked die subsystems are described. A stacked semiconductor package...
US-1,024,9596 Fan-out in ball grid array (BGA) package
In some examples, a device includes at least two integrated circuits (ICs) and a first multi-chip module (MCM) substrate coupled to the at least two ICs, the...
US-1,024,9595 Method of manufacturing a semiconductor device
A non-leaded semiconductor device comprises a sealing body for sealing a semiconductor chip, a tab in the interior of the sealing body, suspension leads for...
US-1,024,9594 Display device and method for assembling the same
The present disclosure provides a display device and a method for assembling the same. The display device includes an electronic device and a flexible printed...
US-1,024,9593 Method for bonding a chip to a wafer
A method for chip on wafer bonding is provided. The method includes the formation of a plurality of posts on at least one of a chip and a wafer, and a like...
US-1,024,9592 Wire bonded wide I/O semiconductor device
A wide I/O semiconductor device is disclosed including a memory die stack wire bonded to an interface chip. The stack of memory die may be wire bonded to the...
US-1,024,9591 Resin composition, bonded body and semiconductor device
A resin composition is provided, including a binder resin, and silver-coated particles in which a functional group is introduced to a surface. A ratio (a/b) of...
US-1,024,9590 Stacked dies using one or more interposers
The present disclosure generally relates to semiconductor structures and, more particularly, to stacked dies using one or more interposers and methods of...
US-1,024,9589 Semiconductor device including conductive layer and conductive pillar disposed on conductive layer and method...
The semiconductor device includes: a semiconductor substrate; a conductor layer formed over the semiconductor substrate and having an upper surface and a lower...
US-1,024,9588 Designs and methods for conductive bumps
Methods, techniques, and structures relating to die packaging. In one exemplary implementation, a die package interconnect structure includes a semiconductor...
US-1,024,9587 Semiconductor device including optional pad interconnect
A semiconductor device is disclosed including semiconductor die formed with functionally redundant main and optional die bond pads. In examples, the optional...
US-1,024,9586 Mixed UBM and mixed pitch on a single die
Embodiments are directed to a method of forming a semiconductor chip package and resulting structures having a mixed under-bump metallization (UBM) size and...
US-1,024,9585 Stackable semiconductor package and manufacturing method thereof
A stackable semiconductor package and manufacturing method thereof are provided. The stackable semiconductor package includes carrier, first RDL, encapsulation...
US-1,024,9584 Semiconductor device and method of manufacturing a semiconductor device
A semiconductor device includes: a substrate; a wiring formed above the substrate; a titanium nitride film formed on the wiring; an oxide film formed on the...
US-1,024,9583 Semiconductor die bond pad with insulating separator
A semiconductor die includes a last metallization layer above a semiconductor substrate, a bond pad above the last metallization layer, a passivation layer...
US-1,024,9582 Radio frequency (RF) devices with resonant circuits to reduce coupling
The embodiments described herein use resonant circuits to provide isolation between closely proximate conductors. For example, these resonant circuits can be...
US-1,024,9581 Transmission line for 3D integrated circuit
A semiconductor transmission line substructure and methods of transmitting RF signals are described. The semiconductor transmission line substructure can...
US-1,024,9580 Stacked substrate inductor
In conventional device packages, separate standalone inductors are provided and mounted on an interposer substrate along with a die. Separate inductors reduce...
US-1,024,9579 Active shield for protecting a device from backside attacks
An electronic apparatus includes, a substrate, one or more routing layers, and an active shield layer. The substrate includes active devices. The routing layers...
US-1,024,9578 Core-shell particles for anti-tampering applications
Devices and methods for resisting or preventing physical tampering of electronic components are described. A tamper resistant apparatus comprises a tampering...
US-1,024,9577 Method of forming metal interconnection and method of fabricating semiconductor apparatus using the method
A semiconductor manufacturing method includes depositing a low-k dielectric layer, forming a trench in the low-k dielectric layer, forming a barrier layer in...
US-1,024,9576 Cavity formation using sacrificial material
A method for fabricating a semiconductor device involves providing a semiconductor substrate, forming an oxide layer in the semiconductor substrate, forming a...
US-1,024,9575 Radio-frequency isolation using cavity formed in interface layer
A method for fabricating a semiconductor device involves providing a transistor device, forming one or more electrical connections to the transistor device,...
US-1,024,9574 Method for manufacturing a seal ring structure to avoid delamination defect
A method for manufacturing a semiconductor device includes providing a semiconductor substrate, forming a plurality of integrated circuit (IC) devices on the...
US-1,024,9573 Semiconductor device package with a stress relax pattern
A semiconductor device package has a die, a pattern of dielectric material formed on an active surface of the die, a plurality of metal contacts electrically...
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