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Patent # Description
US-1,024,9572 Method for electromagnetic shielding and thermal management of active components
The present invention concerns a method for forming a metal layer for electromagnetic shielding and thermal management of active components, preferably by wet...
US-1,024,9571 Thin film transistor and manufacturing method thereof, array substrate, and display panel
A thin film transistor comprises an active layer; a light-protection layer disposed above the active layer and/or disposed beneath the active layer, the...
US-1,024,9570 Overlay mark
An overlay mark includes a first feature of a plurality of first alignment segments extending along a first direction in a first layer, a second feature of a...
US-1,024,9568 Method for making semiconductor device with stacked analog components in back end of line (BEOL) regions
A method for making a semiconductor device may include forming a first dielectric layer above a semiconductor substrate, forming a first trench in the first...
US-1,024,9567 Redistribution layer structure of semiconductor package
A redistribution layer structure of the semiconductor package includes a dielectric layer having a thickness, at least one upper conductive wire disposed on a...
US-1,024,9566 Semiconductor device including fuse structure
An eFuse structure of a semiconductor device may include a first metal formed at a first level on a substrate, a second metal formed at a second level between...
US-1,024,9565 Semiconductor device that transfers an electric signal with a set of inductors
A semiconductor chip is mounted on a first surface of an interconnect substrate, and has a multilayer interconnect layer. A first inductor is formed over the...
US-1,024,9564 Electronic component mounting substrate, electronic device, and electronic module
An electronic component mounting substrate includes an insulating base having a rectangular shape in plan view and including a first main surface, a second main...
US-1,024,9563 Multilayer wiring substrate
Provided is a multilayer wiring substrate capable of achieving excellent conduction reliability. The multilayer wiring substrate is formed by laminating an...
US-1,024,9562 Package structure and fabrication method thereof
A method for fabricating a package structure is provided, which includes the steps of: providing a carrier having a recess; disposing an electronic element in...
US-1,024,9561 Printed wiring board having embedded pads and method for manufacturing the same
A printed wiring board includes a support plate, and a build-up wiring layer including resin insulating layers and conductor layers and having a first surface...
US-1,024,9560 Semiconductor device, system in package, and system in package for vehicle
The object is to suppress rupture of the soldering balls when an atmosphere varying from a high temperature to a low temperature is repeated. A semiconductor...
US-1,024,9559 Ball grid array and land grid array assemblies fabricated using temporary resist
Ball grid assembly (BGA) bumping solder is formed on the back side of a laminate panel within a patterned temporary resist. Processes such as singulation and...
US-1,024,9558 Electronic part mounting heat-dissipating substrate
An electronic heat-dissipating substrate including: lead frames of wiring pattern shapes on a conductor plate; and an insulating member between the lead frames....
US-1,024,9557 Packaged integrated circuit device and methods
A packaged lead frame includes a encapsulant having a first minor side, a second minor side opposite the first minor side, a third minor side, and a fourth...
US-1,024,9556 Lead frame with partially-etched connecting bar
A lead frame strip includes an array of lead frames. The lead frames each include a die pad and lead fingers that are spaced from the die pads and disposed...
US-1,024,9555 Composite heat sink structures
Composite heat sink structures and methods of fabrication are provided, with the composite heat sink structures including: a thermally conductive base having a...
US-1,024,9554 Heat transfer assembly for a heat emitting device
A heat transfer assembly useful for dissipating heat from the heat emitting device is disclosed. The assembly includes a module inlet for receiving a coolant,...
US-1,024,9552 Semiconductor package having double-sided heat dissipation structure
The present disclosure relates to a semiconductor package having a double-sided heat dissipation structure, and more particularly, to a semiconductor package...
US-1,024,9551 Electronic component having a heat-sink thermally coupled to a heat-spreader
An electronic component includes one or more semiconductor dice embedded in a first dielectric layer, a heat-spreader embedded in a second dielectric layer and...
US-1,024,9550 Power module with lead component and manufacturing method thereof
The present invention provides a power module and a manufacturing method thereof. The power module includes a carrier board and a lead component stacked...
US-1,024,9549 Ceramic circuit board, electronic circuit module, and method for manufacturing electronic circuit module
A ceramic circuit board that includes a ceramic insulator layer, grounding pattern conductors, connection lands disposed on a first surface of the ceramic...
US-1,024,9548 Test cell for laminate and method
A laminate includes a plurality of buildup layers disposed on a core and a plurality of unit cells defined in the buildup layers. Each unit cell includes: at...
US-1,024,9547 Method for using a test wafer by forming modified layer using a laser beam and observing damage after forming...
Disclosed herein is a using method for a test wafer including a test substrate and a metal foil formed on the front side of the test substrate. The using method...
US-1,024,9546 Reverse decoration for defect detection amplification
Reverse decoration can be used to detect defects in a device. The wafer can include NAND stacks or other devices. The defect can be a channel bridge, a void, or...
US-1,024,9545 Method for processing substrate including forming a film on a silicon-containing surface of the substrate to...
A method for processing a substrate exposes a silicon-containing surface at a circumferential edge portion of a first main surface of a substrate to be...
US-1,024,9544 Method of inspecting surface and method of manufacturing semiconductor device
Provided are a method of inspecting a surface and a method of manufacturing a semiconductor device. The methods include preparing a substrate, selecting a...
US-1,024,9543 Field effect transistor stack with tunable work function
A method for fabricating a gate stack of a semiconductor device comprises forming a first dielectric layer over a channel region of the device, forming a first...
US-1,024,9542 Self-aligned doping in source/drain regions for low contact resistance
Embodiments are directed to a method of forming a semiconductor device and resulting structures having reduced source/drain contact resistance. The method...
US-1,024,9541 Forming a hybrid channel nanosheet semiconductor structure
A method for fabricating a nanosheet semiconductor structure includes forming a first nanosheet field effect transistor (FET) structure having a first inner...
US-1,024,9540 Dual channel CMOS having common gate stacks
Embodiments are directed to a method and resulting structures for a dual channel complementary metal-oxide-semiconductor (CMOS) having common gate stacks. A...
US-1,024,9539 Nanosheet transistors having different gate dielectric thicknesses on the same chip
Embodiments are directed to a method and resulting structures for forming thin and thick gate dielectric nanosheet transistors on the same chip. A first...
US-1,024,9538 Method of forming vertical field effect transistors with different gate lengths and a resulting structure
Disclosed is a method of forming a structure with multiple vertical field effect transistors (VFETs). In the method, lower source/drain regions are formed on a...
US-1,024,9537 Method and structure for forming FinFET CMOS with dual doped STI regions
A method of making a semiconductor device includes forming a first fin of a first transistor in a substrate; forming a second fin of a second transistor in the...
US-1,024,9536 Semiconductor fins for FinFET devices and sidewall image transfer (SIT) processes for manufacturing the same
A method of forming a semiconductor structure includes providing a semiconductor substrate, forming at least one precursor semiconductor fin from the...
US-1,024,9535 Forming TS cut for zero or negative TS extension and resulting device
A method of forming a logic or memory cell with less than or equal to 0 nm of TS extending past the active fins and the resulting device are provided....
US-1,024,9534 Method of forming a contact element of a semiconductor device and contact element structure
The present disclosure provides a contact element of a semiconductor device structure, wherein an opening is formed in an insulating material layer, the...
US-1,024,9533 Method and structure for forming a replacement contact
A method for manufacturing a semiconductor device includes forming a plurality of gate structures spaced apart from each other on a fin, forming an inorganic...
US-1,024,9532 Modulating the microstructure of metallic interconnect structures
Tooling apparatus and methods are provided to fabricate semiconductor devices in which controlled thermal annealing techniques are utilized to modulate...
US-1,024,9531 Method for forming metal wiring
A method for forming a metal wiring according to embodiments includes forming a first insulating layer on a substrate; forming a catalyst adsorption layer by...
US-1,024,9530 Interlayer dielectric film in semiconductor devices
A method of forming a semiconductor device includes depositing a flowable dielectric layer on a substrate and annealing the flowable dielectric layer. The...
US-1,024,9529 Channel silicon germanium formation method
A method of making a channel region in a semiconductor device includes providing a substrate having a first transistor area arranged adjacent to a second...
US-1,024,9528 Integrated circuit and manufacturing method thereof
An integrated circuit includes a first insulation layer, a bottom plate, a first patterned dielectric layer, a medium plate, a second patterned dielectric...
US-1,024,9527 Method of manufacturing flexible display device
Methods for manufacturing a flexible display device are provided. A flexible substrate is provided and a first bonding pattern, which encloses a display area,...
US-1,024,9526 Substrate support assembly for high temperature processes
An electrostatic chuck comprises a ceramic body having a top and a bottom, one or more heating elements disposed in the ceramic body, and one or more electrodes...
US-1,024,9525 Dynamic leveling process heater lift
A method and apparatus for of improving processing results in a processing chamber by orienting a substrate support relative to a surface within the processing...
US-1,024,9524 Cassette holder assembly for a substrate cassette and holding member for use in such assembly
The invention relates to a cassette holder assembly for holding a cassette for storing at least one semiconductor material substrate in an interior space...
US-1,024,9523 Overlay and semiconductor process control using a wafer geometry metric
The present invention may include acquiring a wafer shape value at a plurality of points of a wafer surface at a first and second process level, generating a...
US-1,024,9522 In-situ temperature measurement in a noisy environment
Disclosed are method and apparatus for treating a substrate. The apparatus is a dual-function process chamber that may perform both a material process and a...
US-1,024,9521 Wet-dry integrated wafer processing system
An apparatus for processing wafer-shaped articles comprises a vacuum transfer module and an atmospheric transfer module. A first airlock interconnects the...
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