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Patent # Description
US-1,024,8602 Computing devices having slots and components for receipt of different types of peripherals
Computing devices having slots and components for receipt of different types of peripherals are disclosed. According to an aspect, a computing device includes a...
US-1,024,8601 Remote terminal unit (RTU) with universal input/output (UIO) and related method
A system includes at least one industrial control and automation field device and a remote terminal unit (RTU). The RTU includes input/output (I/O) terminals...
US-1,024,8600 Remote control system
A remote control system includes computing boards and a control board. The control board includes a first network physical layer protocol conversion chip, a...
US-1,024,8599 USB connections
A method of configuring a Universal Serial Bus (USB) connection between a first and second devices, the USB connection comprising a plurality of data channels,...
US-1,024,8598 Intelligent storage device signal transmission method for backing up data on intelligent storage module based...
An intelligent storage device signal transmission method includes steps of: electrically connecting intelligent storage module and electronic device; enabling...
US-1,024,8597 USB communication control module, security system, and method for same
A security system having a control unit in communication with detection devices and notification systems to provide messages. Methods for employing a control...
US-1,024,8596 Systems and methods for providing a lower-latency path in a virtualized software defined storage architecture
In accordance with embodiments of the present disclosure, a method may include receiving an input/output command from an application executing on a virtual...
US-1,024,8595 Virtual machine monitor interrupt support for computer processing unit (CPU)
An interrupt interface of a central processing unit (CPU) comprises a bus with a plurality of interfaces to various components of the CPU. These components can...
US-1,024,8594 Programming interruption management
The present disclosure is related to programming interruption management. An apparatus can be configured to detect an interruption during a programming...
US-1,024,8593 Techniques for handling interrupts in a processing unit using interrupt request queues
A technique for handling interrupts in a data processing system includes receiving, at an interrupt presentation controller (IPC), an event notification message...
US-1,024,8592 Interrupted write operation in a serial interface memory with a portion of a memory address
Subject matter disclosed herein relates to read and write processes of a memory device.
US-1,024,8591 High performance interconnect
A physical layer (PHY) is coupled to a serial, differential link that is to include a number of lanes. The PHY includes a transmitter and a receiver to be...
US-1,024,8590 Supporting different types of memory devices based on serial presense detect
A computing system for supporting a plurality of different types of memory devices includes a memory voltage regulator. The memory voltage regulator adjusts a...
US-1,024,8589 Integrated circuit with a serial interface
An integrated circuit coupled to an external serial bus is presented. A method for prefetching data from an external serial bus is presented. The integrated...
US-1,024,8588 Frame reception monitoring method in serial communications
The present disclosure relates to a frame reception monitoring method, including: when a plurality of sub-frames constituting a frame is each entered into a...
US-1,024,8587 Reduced host data command processing
Methods and systems are provided that execute reduced host data commands. A reduced host data command may be a write command that includes or is received with...
US-1,024,8585 System and method for filtering field programmable gate array input/output
Systems and methods for adding a logic layer between FPGA I/O and the core logic of the FPGA. With the extra layer, users can monitor and/or modify the I/O to...
US-1,024,8584 Data transfer between host and peripheral devices
A device, which may be a peripheral device or a host computing device, comprises a communication interface, a memory and a processor. The processor is arranged...
US-1,024,8583 Simultaneous video and bus protocols over single cable
Method and systems are disclosed for transporting simultaneous video and bus protocols over a single cable. At least some of the illustrative embodiments are...
US-1,024,8582 Primary data storage system with deduplication
The invention is directed to a primary data storage system for use in a computer network in which a network allows user computers to transfer data to and/or...
US-1,024,8581 Guarded memory access in a multi-thread safe system level modeling simulation
Methods, systems, and machine readable medium for multi-thread safe system level modeling simulation (SLMS) of a target system on a host system. An example of a...
US-1,024,8580 Method and circuit for protecting and verifying address data
A circuit is for protecting memory address data. The circuit may include an input data bus configured to receive write data to be written to a memory device,...
US-1,024,8579 Method, apparatus, and instructions for safely storing secrets in system memory
Embodiments of an invention for method, apparatus, and instructions for safely storing secrets in system memory are disclosed. In one embodiment, a processor...
US-1,024,8578 Methods and systems for protecting data in USB systems
The various embodiments described below are directed to providing authenticated and confidential messaging from software executing on a host (e.g. a secure...
US-1,024,8577 Using a characteristic of a process input/output (I/O) activity and data subject to the I/O activity to...
Provided are a computer program product, system, and method for detecting a security breach in a system managing access to a storage. Process Input/Output (I/O)...
US-1,024,8576 DRAM/NVM hierarchical heterogeneous memory access method and system with software-hardware cooperative management
The present invention provides a DRAM/NVM hierarchical heterogeneous memory system with software-hardware cooperative management schemes. In the system, NVM is...
US-1,024,8575 Suspending translation look-aside buffer purge execution in a multi-processor environment
Disclosed herein is a method for operating translation look-aside buffers, TLBs, in a multiprocessor system. A purge request is received for purging one or more...
US-1,024,8574 Input/output translation lookaside buffer prefetching
Embodiments of apparatuses, methods, and systems for input/output translation lookaside buffer (IOTLB) prefetching are described. In an embodiment, an apparatus...
US-1,024,8573 Managing memory used to back address translation structures
Managing memory of a computing environment. A determination is made as to whether a block of memory is being used to back an address translation structure used...
US-1,024,8572 Apparatus and method for operating a virtually indexed physically tagged cache
An apparatus and method are provided for operating a virtually indexed, physically tagged cache. The apparatus has processing circuitry for performing data...
US-1,024,8571 Saving position of a wear level rotation
In one example in accordance with the present disclosure, a system may include a wear level handler to start a current rotation of a wear level algorithm...
US-1,024,8570 Methods, systems and apparatus for predicting the way of a set associative cache
A method for predicting a way of a set associative shadow cache is disclosed. As a part of a method, a request to fetch a first far taken branch instruction of...
US-1,024,8569 Pattern based preload engine
A method includes obtaining a trigger instruction responsive to execution of an application reaching a specific location and state, wherein the trigger...
US-1,024,8568 Efficient data transfer between a processor core and an accelerator
A processor writes input data to a cache line of a shared cache, wherein the input data is ready to be operated on by an accelerator. It then notifies an...
US-1,024,8567 Cache coherency for direct memory access operations
Methods, apparatus, systems and articles of manufacture are disclosed to maintain cache coherency. Examples disclosed herein involve, in response to receiving,...
US-1,024,8565 Hybrid input/output coherent write
Aspects include computing devices, apparatus, and methods implemented by the apparatus for implementing a hybrid input/output (I/O) coherent write request on a...
US-1,024,8564 Contended lock request elision scheme
A system and method for network traffic management between multiple nodes are described. A computing system includes multiple nodes connected to one another....
US-1,024,8563 Efficient cache memory having an expiration timer
In one embodiment, a method includes selectively invalidating data stored in at least one cache line of a cache memory of a processor in response to a...
US-1,024,8562 Cost-based garbage collection scheduling in a distributed storage environment
In an embodiment, a partition cost of one or more of the plurality of partitions and a data block cost for one or more data blocks that may be subjected to a...
US-1,024,8561 Stateless detection of out-of-memory events in virtual machines
The disclosed embodiments provide a system that detects anomalous events in a virtual machine. During operation, the system obtains time-series ...
US-1,024,8560 Storage device that restores data lost during a subsequent data write
A storage device that can be connected to a host device includes a plurality of nonvolatile memories. Each nonvolatile memory includes first memory cells...
US-1,024,8559 Weighting-type data relocation control device and method
The present disclosure provides a weighting-type data relocation control device for controlling data relocation of a non-volatile memory which includes used...
US-1,024,8558 Memory leakage power savings
In some aspects, a method for managing leakage power includes coupling a first supply rail to a cache memory if a processor is in a first performance mode,...
US-1,024,8557 Systems and methods for delayed allocation in cluster storage
The disclosed computer-implemented method for delayed allocation in cluster storage may include (i) delegating, to a node attached to a storage cluster...
US-1,024,8556 Forward-only paged data storage management where virtual cursor moves in only one direction from header of a...
Computer-implemented methods and systems for managing data in one or more data storage media are provided. An example method may comprise creating a data...
US-1,024,8555 Managing an effective address table in a multi-slice processor
Methods and apparatus for managing an effective address table (EAT) in a multi-slice processor including receiving, from an instruction sequence unit, a...
US-1,024,8554 Embedding profile tests into profile driven feedback generated binaries
Aspects of the present invention include a method, system and computer program product that embeds collected profiling test case information into a binary file...
US-1,024,8553 Test methodology for detection of unwanted cryptographic key destruction
A test program is run repeatedly (either as a loop that is programmed into the code of the test program itself, or by repeatedly running the test program...
US-1,024,8552 Generating test scripts for testing a network-based application
There is provided a computer-implemented method of testing an application. The method obtains first temporary test scripts for testing at least one test case of...
US-1,024,8551 Selective object testing in a client-server environment
A tool for testing objects in a client-server environment. The tool receives a plurality of proposed modifications to a baseline set of objects stored in a...
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