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Patent # Description
US-1,025,6340 High-voltage semiconductor device and method for manufacturing the same
A high-voltage semiconductor device is provided. The device includes a semiconductor substrate having a first conductivity type, and a first doping region...
US-1,025,6339 Semiconductor device for power transistor
In a semiconductor device, in a gate insulating film which is formed on/over an inner wall of a trench, the film thickness of a part of a gate insulating film...
US-1,025,6338 Semiconductor device and method of manufacturing semiconductor device
A semiconductor device includes a semiconductor substrate, a first epitaxial layer of a first conductivity type, a first semiconductor region of the first...
US-1,025,6337 Power transistor with terminal trenches in terminal resurf regions
A device includes a transistor formed on a substrate. The transistor includes an n-type drain contact layer, an n-type drain layer, an oxide layer, a p-type...
US-1,025,6336 Semiconductor device
A semiconductor device is provided with an N.sup.--type drift layer, a P.sup.+-type diffusion well region provided on a surface part of the N.sup.--type drift...
US-1,025,6335 Nitride semiconductor device and fabrication method therefor
A nitride semiconductor device includes an electron transit layer (103) that is formed of a nitride semiconductor, an electron supply layer (104) that is formed...
US-1,025,6334 Gateless switch with capacitively-coupled contacts
A switch includes an input contact and an output contact to a conducting channel. At least one of the input and output contacts is capacitively coupled to the...
US-1,025,6333 High electron mobility transistor
The embodiments of the present invention disclose a high electron mobility transistor, comprising: a substrate; a channel layer located on the substrate; a...
US-1,025,6332 High hole mobility transistor
A high hole mobility transistor includes a substrate, a back-barrier layer, a conducting layer, a doping layer, a gate electrode, source/drain electrodes, and a...
US-1,025,6331 Insulated gate turn-off device having low capacitance and low saturation current
An insulated gate turn-off (IGTO) device, formed as a die, has a layered structure including a P+ layer (e.g., a substrate), an N- epi layer, a P-well, vertical...
US-1,025,6330 Switching circuit
A switching circuit may be provided with: a parallel circuit including a first IGBT and a second IGBT connected in parallel; a controller configured to receive...
US-1,025,6329 Heterojunction bipolar transistor
A HBT on a GaAs substrate is presented, wherein its base comprises a first base layer comprising In.sub.iGa.sub.1-iAs with an Indium content i with a slope s1...
US-1,025,6328 Dummy dielectric fins for finFETs with silicon and silicon germanium channels
A method for forming a semiconductor device includes forming first fins from a first semiconductor material and second fins from a second semiconductor material...
US-1,025,6327 Forming a fin using double trench epitaxy
The present invention relates generally to semiconductor devices and more particularly, to a structure and method of forming a fin using double trench epitaxy....
US-1,025,6326 Forming stacked nanowire semiconductor device
A semiconductor device comprises a nanowire arranged over a substrate, a gate stack arranged around the nanowire, a spacer arranged along a sidewall of the gate...
US-1,025,6325 Radiation-hardened power semiconductor devices and methods of forming them
According to an embodiment, a method of forming a power semiconductor device is provided. The method includes providing a semiconductor substrate and forming an...
US-1,025,6324 Semiconductor devices having vertical transistors with aligned gate electrodes
A semiconductor device includes an active pillar on a substrate. A first source/drain region is disposed at a top end of the active pillar and has a greater...
US-1,025,6323 Method of manufacturing semiconductor device including an n type semiconductor region formed in a p type...
A technique of improving the breakdown voltage of a semiconductor device is provided. There is provided a method of manufacturing a semiconductor device...
US-1,025,6322 Co-doping process for n-MOS source drain application
A device comprising Si:As source and drain extensions and Si:As or Si:P source and drain features formed using selective epitaxial growth and a method of...
US-1,025,6321 Semiconductor device including enhanced low-k spacer
A semiconductor device includes a semiconductor substrate including a channel region and a source/drain region, and an electrically conductive gate on an upper...
US-1,025,6320 Vertical field-effect-transistors having a silicon oxide layer with controlled thickness
A vertical field-effect transistor and a method for fabricating the same. The vertical field-effect transistor includes a substrate and a bottom source/drain...
US-1,025,6319 Non-uniform gate dielectric for U-shape MOSFET
A U-shaped gate dielectric structure is provided that has a horizontal gate dielectric portion having a vertical thickness, and a vertical gate dielectric wall...
US-1,025,6318 Method of manufacturing semiconductor device to prevent defects
A method of manufacturing a semiconductor device includes forming dummy gate structures including a dummy gate insulating layer and dummy gate electrodes, on a...
US-1,025,6317 Vertical transistor gated diode
After forming a trench extending through a sacrificial gate layer to expose a surface of a doped bottom semiconductor layer, a diode including a first doped...
US-1,025,6316 Steep-switch field effect transistor with integrated bi-stable resistive system
Fabricating a steep-switch transistor includes receiving a semiconductor structure including a substrate, a fin disposed on the substrate, a source/drain...
US-1,025,6315 Thin film transistor and method for fabricating the same, array substrate and display device
A thin film transistor, a method for fabricating the same, an array substrate, and a display device are provided. The thin film transistor comprises a copper...
US-1,025,6314 Semiconductor device
A semiconductor device includes a first semiconductor layer, a first electrode above and electrically connected to the first semiconductor layer, a second...
US-1,025,6313 Semiconductor device with surface insulating film
A semiconductor device of the present invention includes a semiconductor layer of a first conductivity type having a cell portion and an outer peripheral...
US-1,025,6312 Semiconductor structure with a gap between conductor features and fabrication method thereof
A semiconductor structure includes a contact plug located on a barrier layer in a contact hole; a first conductive feature integrally formed with the contact...
US-1,025,6311 Fin field effect transistor (FinFET)
A fin field effect transistor (FinFET) is provided. The FinFET includes a first gate having top and bottom portions of different widths, the top portion of the...
US-1,025,6310 Split-gate flash memory cell having a floating gate situated in a concave trench in a semiconductor substrate
A split-gate flash memory cell is provided. The split-gate flash memory cell includes a semiconductor substrate having a source region and a drain region. The...
US-1,025,6309 Memory cells having electrically conductive nanodots
Memory cells having electrically conductive nanodots between a charge storage material and a control gate are useful in non-volatile memory devices and...
US-1,025,6308 Semiconductor device, power supply circuit, and computer
A semiconductor device according to an embodiment includes a first nitride semiconductor layer; a second nitride semiconductor layer on the first nitride...
US-1,025,6307 Semiconductor device
A semiconductor device is provided. The semiconductor device includes a first doped region and a second doped region of a first conductive type and a third...
US-1,025,6306 Vertically integrated multispectral imaging sensor with graphene as electrode and diffusion barrier
A vertically integrated multispectral imaging sensor includes a first metal contact layer on a substrate, an SiO.sub.2 layer on the first metal contact layer...
US-1,025,6305 High mobility transport layer structures for rhombohedral Si/Ge/SiGe devices
An electronic device includes a trigonal crystal substrate defining a (0001) C-plane. The substrate may comprise Sapphire or other suitable material. A...
US-1,025,6303 Semiconductor device
Provided is a semiconductor device including a plurality of dummy trench portions that are provided in a front surface side of a semiconductor substrate and...
US-1,025,6302 Vertical transistor with air-gap spacer
A vertical transistor has a first air-gap spacer between a gate and a bottom source/drain region, and a second air-gap spacer between the gate and the contact...
US-1,025,6301 Nanosheet isolated source/drain epitaxy by surface treatment and incubation delay
A semiconductor device includes a plurality of stacked structures spaced apart from each other on a substrate, wherein the plurality of stacked structures each...
US-1,025,6300 Semiconductor device
A semiconductor device includes: an active layer that is located in an SOI substrate, and in which an element included in a circuit is formed; a buried...
US-1,025,6299 SOI island in a power semiconductor device
A power semiconductor device includes a semiconductor-on-insulator island having a semiconductor region and an insulation structure, the insulation structure...
US-1,025,6298 Semiconductor structure and method for forming the same
A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a substrate and a semiconductor layer formed on...
US-1,025,6297 Semiconductor device and method for fabricating the same
A method for fabricating semiconductor device includes the steps of first providing a substrate, forming a gate structure on the substrate, forming a hard mask...
US-1,025,6296 Middle-of-line (MOL) capacitance reduction for self-aligned contact in gate stack
A semiconductor structure formed based on selectively recessing a middle-of-line (MOL) oxide layer of the semiconductor structure including multiple gate stacks...
US-1,025,6295 Semiconductor device
A semiconductor device includes an outside-of-well n-type region, a p-type well region surrounded by the outside-of-well n-type region, an inside-of-well n-type...
US-1,025,6294 Vertical gallium nitride power field-effect transistor with a field plate structure
The present disclosure relates to a vertical gallium-nitride (GaN) power field-effect transistor (FET) with a field plate structure. The vertical GaN power FET...
US-1,025,6293 Integrated circuit devices having features with reduced edge curvature and methods for manufacturing the same
A structure such as an integrated circuit device is described having a line of material with critical dimensions which vary within a distribution substantially...
US-1,025,6292 Vertical MOSFET
In order to improve the dynamic characteristics of a vertical MOSFET using GaN, it is an objective of the present invention to reduce the resistance of a...
US-1,025,6291 Method of manufacturing semiconductor device
An object is to provide a method for manufacturing a highly reliable semiconductor device including a transistor with stable electric characteristics. A method...
US-1,025,6290 Method for oxidizing a substrate surface using oxygen
A method for treating a compound semiconductor substrate, in which method in vacuum conditions a surface of an In-containing III-As, III-Sb or III-P substrate...
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