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Patent # Description
US-1,025,6137 Self-aligned trench isolation in integrated circuits
An A method for fabricating an integrated circuit (IC) comprising a substrate, a first device, a second device, and a trench in the substrate is described...
US-1,025,6136 Method of manufacturing isolation structure for semiconductor device
A method for manufacturing a semiconductor device includes forming a first trench and a second trench in a substrate, the first and the second trenches...
US-1,025,6135 Semiconductor device and method of manufacturing semiconductor device
To provide a semiconductor device having a substrate contact in a deep trench thereof and having an improved characteristic. A PVD-metal film (metal film formed...
US-1,025,6134 Heat dissipative element for polysilicon resistor bank
An integrated circuit (IC) structure is disclosed. The structure can include: a first heat dissipative element disposed between a pair of shallow trench...
US-1,025,6133 Method of manufacturing semiconductor device
To improve the characteristics of a semiconductor device having a substrate contact formed in a deep trench. In a method of forming a plug PSUB in a deep trench...
US-1,025,6132 Reticle processing system
Provided herein are approaches for processing reticle blanks. In one approach, a reticle processing system includes a support assembly having a plate coupled to...
US-1,025,6131 Electrostatic chuck device
An electrostatic chuck device includes an electrostatic chuck member and a temperature controlling base member. The electrostatic chuck member has a ceramic...
US-1,025,6130 Electrostatic holding device and method for the operation thereof, and charge transfer circuit
An electrostatic holding device (100) for holding component (1) by electrostatic holding forces includes clamp carrier (10) which has electrode device (11) and...
US-1,025,6129 Carrier buffering device and buffering method
A temporary storage apparatus is provided with a slidable buffer which does not prevent installation of the apparatus and maintenance of equipment, has...
US-1,025,6128 Cooling mechanism and processing system
A cooling mechanism includes a plurality of support stands which is provided in a vertical direction over a plurality of stages in an atmospheric transfer...
US-1,025,6127 Substrate transfer apparatus, substrate transfer method, and non-transitory storage medium
A substrate transfer apparatus to transfer a circular substrate provided with a cutout at an edge portion thereof, includes: a sensor part including three light...
US-1,025,6126 Gas flow process control system and method using crystal microbalance(s)
Disclosed are process control systems and methods incorporating a crystal microbalance (CM) (e.g., a quartz crystal microbalance (QCM)) into gas flow line(s)...
US-1,025,6125 Wafer processing systems including multi-position batch load lock apparatus with temperature control capability
Various embodiments of wafer processing systems including batch load lock apparatus with temperature control capability are disclosed. The batch load lock...
US-1,025,6124 Method and system related to semiconductor processing equipment
A system including a first linear bearing, a second linear bearing, a first shuttle, and a second shuttle. The first linear bearing is mounted in and disposed...
US-1,025,6123 Component temperature control using a combination of proportional control valves and pulsed valves
Methods and systems for controlling temperatures in plasma processing chamber with a combination of proportional and pulsed fluid control valves. A heat...
US-1,025,6122 Substrate heating method
A substrate heating device includes: heating modules each having a processing vessel within which a heating plate is disposed, an gas inlet port for introducing...
US-1,025,6121 Heated stage with variable thermal emissivity method and apparatus
Embodiments include a method for controlled cooling of a heated stage. The method includes setting a stage coupling to a maximum value and heating the stage to...
US-1,025,6120 Systems, methods and apparatus for post-chemical mechanical planarization substrate buff pre-cleaning
In some embodiments, an apparatus for cleaning a substrate is provided that includes (1) a substrate chuck configured to support a substrate with a front side...
US-1,025,6119 Method of manufacturing a semiconductor power package
A method of manufacturing a semiconductor power package includes: providing a pre-molded chip housing and an electrically conducting chip carrier cast-in-place...
US-1,025,6117 Manufacturing method and wiring substrate with through electrode
There is provided a method for manufacturing a wiring substrate with a through electrode, the method including providing a device substrate having a through...
US-1,025,6116 Process for packaging circuit component having copper circuits with solid electrical and thermal conductivities...
A method for packaging a circuit component, comprising: forming a first protruding pad on a first copper substrate and a through-hole in the first protruding...
US-1,025,6115 Method of manufacturing semiconductor device
A method of manufacturing a semiconductor device may include forming a first stack structure by alternately stacking first material layers and second material...
US-1,025,6114 Semiconductor device with tiered pillar and manufacturing method thereof
A semiconductor device having one or more tiered pillars and methods of manufacturing such a semiconductor device are disclosed. The semiconductor device may...
US-1,025,6113 Transfer substrate for forming metal wiring and method for forming metal wiring with the transfer substrate
A transfer substrate for transferring a metal wiring material to a transfer target including a substrate, at least one metal wiring material formed on the...
US-1,025,6112 Selective tungsten removal
Exemplary methods for removing tungsten-containing material may include flowing a chlorine-containing precursor into a processing region of a semiconductor...
US-1,025,6111 Chemical mechanical polishing automated recipe generation
A method for polishing dies locations on a substrate with a polishing module. A thickness at selected locations on the substrate is premeasured at a metrology...
US-1,025,6110 Self-aligned patterning process utilizing self-aligned blocking and spacer self-healing
A multiple patterning process is provided with a self-aligned blocking (SAB) technique. The SAB technique trades off difficult overlay requirements for more...
US-1,025,6109 Nitrogen-containing compounds for etching semiconductor structures
A method for etching silicon-containing films is disclosed. The method includes the steps of introducing a vapor of a nitrogen containing etching compound into...
US-1,025,6108 Atomic layer etching of AL.sub.2O.sub.3 using a combination of plasma and vapor treatments
A method for performing atomic layer etching (ALE) on a substrate, including the following method operations: performing a surface modification operation on a...
US-1,025,6107 Substrate processing method
There is disclosed a substrate processing method for etching a substrate on which a first and a second silicon oxide layer having different film qualities are...
US-1,025,6106 Sacrificial shorting straps for superconducting qubits
A technique relates to protecting a tunnel junction. A first electrode paddle and a second electrode paddle are on a substrate. The first and second electrode...
US-1,025,6105 Disc-shaped heater and heater-cooling-plate assembly
An electrostatic chuck heater includes a disc-shaped ceramic base and a plurality of heating elements embedded in the ceramic base. A top surface of the...
US-1,025,6104 Film thickness measuring method, film thickness measuring apparatus, polishing method, and polishing apparatus
The present invention relates to a film-thickness measuring method for detecting a film thickness by analyzing optical information contained in a reflected...
US-1,025,6103 Fabrication method for thin film transistor, thin film transistor and display apparatus
The present application discloses a method for fabricating a thin film transistor including the steps of: sequentially forming an active layer, a gate...
US-1,025,6102 Method for fabricating a field effect transistor having a surrounding grid
A process for fabricating a gate-wrap-around field-effect transistor is provided, including providing a substrate surmounted with first and second nanowires...
US-1,025,6101 Raw material gas supply apparatus, raw material gas supply method and storage medium
In a raw material gas supply apparatus, a control unit obtains an offset value of (m3-(m1+m2)), m1, m2 and m3 being respective measurement values of first and...
US-1,025,6100 Manufacturing method of semiconductor device and semiconductor device
The present invention makes it possible to improve the characteristic of a semiconductor device using a nitride semiconductor. An electrically-conductive film...
US-1,025,6099 Transistors having semiconductor-metal composite gate electrodes containing different thickness interfacial...
A semiconductor structure, such as a CMOS device, includes a first field effect transistor and a second field effect transistor. The first field effect...
US-1,025,6098 Integrated assemblies containing germanium
Some embodiments include an integrated assembly having a first semiconductor structure containing heavily-doped silicon, a germanium-containing interface...
US-1,025,6097 Forming a metal contact layer on silicon carbide and semiconductor device with metal contact structure
A semiconductor device includes a silicon carbide semiconductor body and a metal contact structure. Interface particles including a silicide kernel and a carbon...
US-1,025,6096 Self-aligned double patterning
A semiconductor device and a method of forming the same are provided. An embodiment comprises a target layer and masking layers over the target layer. First...
US-1,025,6095 Method for high throughput using beam scan size and beam position in gas cluster ion beam processing system
A system and method for performing location specific processing of a workpiece is described. The method includes placing a microelectronic workpiece in a beam...
US-1,025,6094 Reduction of basal plane dislocations in epitaxial SiC using an in-situ etch process
A method of: providing an off-axis 4H--SiC substrate, and etching the surface of the substrate with hydrogen or an inert gas.
US-1,025,6093 Selective area growth of semiconductors using patterned sol-gel materials
Systems and methods for growing semiconductor materials on substrates by using patterned sol-gel materials are provided. According to a first aspect of the...
US-1,025,6092 Fabrication of semiconductor structures
The invention relates to a method for fabricating a semiconductor circuit comprising providing a semiconductor substrate; fabricating a first semiconductor...
US-1,025,6091 Oxide for semiconductor layer of thin-film transistor, semiconductor layer of thin-film transistor having said...
The oxide of the present invention for thin-film transistors is an In--Zn--Sn-based oxide containing In, Zn, and Sn, wherein when the respective contents...
US-1,025,6090 Reduction of basal plane dislocations in epitaxial SiC using an in-situ etch process
A method of: providing an off-axis silicon carbide substrate, and etching the surface of the substrate with a dry gas, hydrogen, or an inert gas.
US-1,025,6089 Replacement contact cuts with an encapsulated low-K dielectric
Interconnect structures and methods of forming an interconnect structure. A sacrificial contact is arranged between a first gate structure and a second gate...
US-1,025,6088 Device for ion sorting by m/z
An RF voltage is applied across each electrode of a first array of evenly spaced, parallel, and coplanar electrodes and its corresponding electrode of a second...
US-1,025,6087 Band pass extraction from an ion trapping device and TOF mass spectrometer sensitivity enhancement
A multipole rod set of an ion guide is adapted to receive a radial RF trapping voltage and a radial dipole direct current DC voltage. A lens electrode of the...
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