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Patent # Description
US-1,025,5218 Systems and methods for maintaining specific ordering in bus traffic
A system and method for efficiently bridging two communication protocols. In various embodiments, a computing system includes an interconnect for routing...
US-1,025,5217 Two level QoS scheduling for latency and queue depth control
A method for two level quality of service scheduling for latency and queue depth control in a storage system is provided. The method includes determining queue...
US-1,025,5216 Multiplexed memory in a communication processing system
In some examples, a communications device includes a magnetic memory accessible by both a central processing unit and a digital signal processor to enable the...
US-1,025,5215 Enhanced PCIe storage device form factors
Enhanced data storage devices in various form factors are discussed herein. In one example, a storage drive includes a plurality of storage devices configured...
US-1,025,5214 System, methodology, and process for wireless transmission of sensor data onboard an aircraft to a portable...
Monitoring and reporting methods and apparatus include the acquisition of detailed aircraft state and systems data, analysis of the collected data, and...
US-1,025,5213 Adapter device for large address spaces
Provided are methods and adapter devices for buffering write transactions directed to a large space. In various implementations, an adapter device may include a...
US-1,025,5212 Automatic master-slave system and approach
An automatic master slave system and approach for coordinated control of a parameter, for example, a heating, ventilation and air conditioning condition, in an...
US-1,025,5211 Electronic control unit
Provided is an electronic control unit including: a master microcomputer having a master memory (23) that includes a master target data area (A7), a plurality...
US-1,025,5210 Adjusting order of execution of a target device
A master device transmits a transaction to a target device. The transaction includes a transaction identifier. An ordering message is sent to the target device...
US-1,025,5209 Tracking statistics corresponding to data access in a computer system
Embodiments of the present invention disclose a method, computer program product, and system for determining statistics corresponding to data transfer...
US-1,025,5208 Data transfer apparatus and data transfer system
A data transfer apparatus according to an embodiment includes: a first main memory configured to store first data to be used by a first processor; a first hash...
US-1,025,5207 Method and apparatus use with interrupts
A system is configured to capture a set of interrupts and output the interrupts serially onto an interconnect. The interrupts, which are routed to a...
US-1,025,5206 Storage memory direct access
Example implementations relate to a storage memory direct access (SMDA) provider. The SMDA provider may pin a storage memory region to a memory address of a...
US-1,025,5205 System and methods for mixed-signal computing
Systems and methods of implementing a mixed-signal integrated circuit includes sourcing, by a reference signal source, a plurality of analog reference signals...
US-1,025,5204 Key-based data security management
Embodiments of the present invention provide an approach for memory protection at a level of granularity above a "page" level (e.g., enhancing the protection...
US-1,025,5203 Technologies for zero-copy inter-virtual-machine data movement
Technologies for zero-copy inter-virtual-machine communication include a computing device with extended page table support. A sender virtual machine stores data...
US-1,025,5202 Multi-tenant encryption for storage class memory
Various embodiments are generally directed to the providing for mutual authentication and secure distributed processing of multi-party data. In particular, an...
US-1,025,5201 Local key management for storage devices
A method and system provide local key management for storage enclosures. The method includes retrieving first security content from a security vault of a...
US-1,025,5200 Data storage device and method of operation using multiple security protocols
A data storage device includes a memory and a controller that is coupled to the memory. The controller includes an authentication engine, an interface, and an...
US-1,025,5199 Evicting clean secure pages without encryption
Secure memory paging technologies are described. Embodiments of the disclosure may include checking attributes of secure page cache map to determine whether a...
US-1,025,5198 Deferring registration for DMA operations
Systems and methods for deferring registration for Direct Memory Access (DMA) operations. An example method comprises: receiving a memory region registration...
US-1,025,5197 Adaptive tablewalk translation storage buffer predictor
A system for generating predictions for a hardware table walk to find a map of a given virtual address to a corresponding physical address is disclosed. The...
US-1,025,5196 Method and apparatus for sub-page write protection
An apparatus and method for sub-page extended page table protection. For example, one embodiment of an apparatus comprises: a page miss handler to perform a...
US-1,025,5195 Apparatus and method for performing address translation
An apparatus, system, and method for address translation are provided. Physical address information corresponding to virtual addresses is prefetched and stored,...
US-1,025,5194 Configurable I/O address translation data structure
In response to a determination to allocate additional storage, within a real address space employed by a system memory of a data processing system, for...
US-1,025,5193 Virtual address table
The present disclosure includes apparatuses and methods related to virtual address tables. An example method comprises generating an object file that comprises:...
US-1,025,5192 Data storage device and data maintenance method thereof
The present invention provides a data storage device including a flash memory and a controller. The flash memory includes a plurality of blocks, wherein each of...
US-1,025,5191 Logical memory address regions
Systems, apparatuses, and methods for implementing logical memory address regions in a computing system. The physical memory address space of a computing system...
US-1,025,5190 Hybrid cache
Systems, apparatuses, and methods for implementing a hybrid cache. A processor may include a hybrid L2/L3 cache which allows the processor to dynamically adjust...
US-1,025,5189 Mechanism for creating friendly transactions with credentials
A transactional memory execution environment receives a first request from a first transaction to access a cache line. A first request is received from a first...
US-1,025,5188 Migrating workloads across host computing systems based on cache content usage characteristics
Techniques for migrating workloads across host computing systems in a virtual computing environment are described. In one embodiment, workloads executing on...
US-1,025,5187 Systems and methods for implementing weak stream software data and instruction prefetching using a hardware...
A method for weak stream software data and instruction prefetching using a hardware data prefetcher is disclosed. A method includes, determining if software...
US-1,025,5186 Approximate cache memory
An approximate cache system is disclosed. The system includes a quality aware cache controller (QACC), a cache, a quality table configured to receive addresses...
US-1,025,5185 Cache management in a stream computing environment that uses a set of many-core hardware processors
Disclosed aspects relate to cache management in a stream computing environment that uses a set of many-core hardware processors to process a stream of tuples by...
US-1,025,5184 Memory access architecture with coherence
Disclosed aspects relate to a computer system having a plurality of processor chips and a plurality of memory buffer chips, and for transferring data in the...
US-1,025,5183 Victim buffer for cache coherent systems
In accordance with various aspects of the invention, a recall transaction is issued if a tag filter entry needs to be freed up for an incoming transaction....
US-1,025,5182 Computing apparatus and method for cache management
A method of managing a cache includes storing first data of an upper level cache in a lower level cache, predicting a reuse distance level of second data having...
US-1,025,5181 Dynamic input/output coherency
Aspects include computing devices, apparatus, and methods implemented by the apparatus for implementing dynamic input/output (I/O) coherent workload processing...
US-1,025,5180 Server-based persistence management in user space
A persistence management system performs, at a server, operations associated with a number of applications. At the server, a persistence manager can intercept a...
US-1,025,5179 Garbage collection read throttling
A device that provides garbage collection read throttling includes at least one processor that is configured to receive a request to perform a garbage...
US-1,025,5178 Storage device that maintains a plurality of layers of address mapping
A storage device includes a nonvolatile memory, a cache memory, and a processor configured to load, from the nonvolatile memory into the cache memory, a...
US-1,025,5177 System and method for adaptive optimization for performance in solid state drives based on read/write intensity
A method and information handling system and having a solid state drive (SSD) memory device including NAND flash memory with an SSD controller to execute...
US-1,025,5176 Input/output (`I/O`) in a storage system that includes multiple types of storage devices
Writing data in a storage system that includes a first type of storage device and a second type of storage device, including: selecting, for one or more...
US-1,025,5175 Electronic device and memory allocation method therefor
An electronic device according to an embodiment of the present disclosure comprises: a memory including a plurality of pages; and a controller selecting a page...
US-1,025,5174 Common cache pool for applications
A system having a common cache pool (CCP) includes a computing device having a plurality of applications executable on the computing device, each of the...
US-1,025,5173 Experimentation in internet-connected applications and devices
A content variation experiment system for performing variation testing of web pages is disclosed. A content provider receives requests for a web page undergoing...
US-1,025,5172 Controlled testing using code error injection
A computer program product, system, and method for: registering one or more agents within a program, wherein each agent is located along an execution path of...
US-1,025,5171 Test methodology for detection of unwanted cryptographic key destruction
A test program is run repeatedly (either as a loop that is programmed into the code of the test program itself, or by repeatedly running the test program...
US-1,025,5170 On-demand codeset converter generation
A computer-implemented method includes receiving from a codeset compiler a request for a codeset converter to convert from a source codeset to a target codeset....
US-1,025,5169 Testing applications using application features grouped into categories of human senses
A method to test a software application based on grouping application features based on categories of the human mind and human senses. Methods and systems for...
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