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Patent # Description
US-1,025,5117 Task queuing and dispatching mechanisms in a computational device
A plurality of ordered lists of dispatch queues corresponding to a plurality of processing entities are maintained, wherein each dispatch queue includes one or...
US-1,025,5116 Method of redistributing access points automatically to controllers for restoring topology and balancing load
A method, apparatus and computer program product for performing load balancing of SNDs and FNDs is presented. The presently disclosed method and apparatus for...
US-1,025,5115 Generation of directed acyclic graphs from task routines
An apparatus including a processor to: parse comments of multiple task routines to identify I/O parameters; generate a visualization of a DAG to include a...
US-1,025,5114 Abnormality detection apparatus, control method, and program
An abnormality detection apparatus (2000) handles tasks allocated to a plurality of processing servers (3200) as processing targets in a distribution system...
US-1,025,5113 Workload interference estimation and performance optimization
Architecture that facilitates the estimation of interference among workloads (e.g., virtual machines) due to sharing of a shared resource (e.g., a shared cache...
US-1,025,5112 Resource substitution and reallocation in a virtual computing environment
A host system reallocates resources in a virtual computing environment by first receiving a request to reallocate a first quantity of a first resource type....
US-1,025,5111 System and method of deriving appropriate target operating environment
The present invention relates to a configurable parameter driven system and method for providing an appropriate target operating environment based on user...
US-1,025,5110 Node selection for a new application in a multi-tenant cloud hosting environment
A method includes instantiating a first web application for a first application owner on a virtual machine and instantiating a second web application for a...
US-1,025,5109 High bandwidth connection between processor dies
Methods and apparatus relating to techniques for avoiding cache lookup for cold cache. In an example, an apparatus comprises logic, at least partially...
US-1,025,5108 Parallel execution of blockchain transactions
A system, method, and computer readable storage medium for accessing a data file shared by all computing nodes participating in a system based on a blockchain...
US-1,025,5107 Operation of a multi-slice processor implementing a load/store unit maintaining rejected instructions
Operation of a multi-slice processor that includes a plurality of execution slices, a plurality of load/store slices, and one or more instruction sequencing...
US-1,025,5106 Prediction-based power management strategy for GPU compute workloads
A device for processing data includes a processing unit configured to predict an execution time of a compute kernel on a secondary processing unit and, based on...
US-1,025,5105 Parallel computing architecture for use with a non-greedy scheduling algorithm
Methods and architectures for coordinating the operation of a plurality of processing units in a parallel computing architecture wherein each processing unit is...
US-1,025,5104 System call queue between visible and invisible computing devices
Embodiments described herein include a system, a computer-readable medium and a computer-implemented method for processing a system call (SYSCALL) request. The...
US-1,025,5103 Transaction handling
Transaction handling apparatus comprises a response buffer; and tracking circuitry to store data defining each transaction issued by one or more transaction...
US-1,025,5102 Transaction control arrangement for device management system
A method includes providing device management services to by defining one or more transaction control primitives and one or more transaction initiation commands...
US-1,025,5101 Device emulator
The disclosure generally describes computer-implemented methods, software, and systems, including a method for emulating a device. A set of current external...
US-1,025,5100 Performance optimization engine for processor parameter adjustment
A method for processor parameter adjustment using a performance optimization engine is provided. An aspect includes receiving, by the performance optimization...
US-1,025,5099 Guest-influenced packet transmission
A method performed by a physical computing system includes, with a hypervisor, receiving a first packet from a virtual machine managed by the hypervisor, the...
US-1,025,5098 Administering virtual machines in a distributed computing environment
In a distributed computing environment that includes hosts that execute a VMM, where each VMM supports execution of one or more VMs, administering VMs may...
US-1,025,5097 Administering virtual machines in a distributed computing environment
In a distributed computing environment that includes hosts that execute a VMM, where each VMM supports execution of one or more VMs, administering VMs may...
US-1,025,5096 Temporal dynamic virtual machine policies
Temporal dynamic policies may be used to effectively alter the management of a virtual machine in a virtualized computing environment based upon some temporal...
US-1,025,5095 Temporal dynamic virtual machine policies
Temporal dynamic policies may be used to effectively alter the management of a virtual machine in a virtualized computing environment based upon some temporal...
US-1,025,5094 Utilizing physical systems and virtual systems for virtual network functions
A method includes provisioning a first Virtual Network Function (VNF) component on a first virtual machine, the first virtual machine being supported by a first...
US-1,025,5093 Techniques for portable computing device virtualization
Various embodiments are generally directed to providing virtualization using relatively minimal processing and storage resources to enable concurrent isolated...
US-1,025,5092 Managed virtual machine deployment
A system can include computer instructions that can cause a computing device to obtain a request to access an application on behalf of a user. The request can...
US-1,025,5091 Adaptive CPU NUMA scheduling
Systems and methods for performing selection of non-uniform memory access (NUMA) nodes for mapping of virtual central processing unit (vCPU) operations to...
US-1,025,5090 Hypervisor context switching using a redirection exception vector in processors having more than two...
In a virtualized computer system operable in more than two hierarchical privilege levels, components of a hypervisor, which include a virtual machine kernel and...
US-1,025,5089 Self-deleting virtual machines
Securing a virtual machine to be executed on a host machine is accomplished by authenticating, by the virtual machine during an initial boot routine, an...
US-1,025,5088 Modification of write-protected memory using code patching
Systems and methods are provided for modifying a set of memory pages. An example method includes loading kernel code and patching code of a kernel into a guest...
US-1,025,5087 Dynamic I/O virtualization system having a bidirectional extended hybrid address space (EHAS) for allowing host...
A system and method for providing dynamic I/O virtualization is herein disclosed. According to one embodiment, a device capable of performing ...
US-1,025,5086 Determining optimal methods for creating virtual machines
A computer receives at least one requirement for a new VM. The computer identifies an existing VM to be modified during the generation of the new VM. The...
US-1,025,5085 Interactive graphical user interface with override guidance
One exemplary system can receive a selection of a dataset via a graphical user interface (GUI). The dataset can represent a time-series projection. The system...
US-1,025,5084 Manage analytics contexts through a series of analytics interactions via a graphical user interface
The present disclosure relates to an interactive system that manages analytics contexts through a series of analytics interactions. The disclosed interactive...
US-1,025,5083 Method and system for unified input in cross-platform streaming applications in cloud computing environments
A computer program, method, and system for cross-platform input data unification. According to some embodiments, a first input data is received from a first...
US-1,025,5082 Video monitoring
One or more computing devices, systems, and/or methods for monitoring a video are provided. For example, the video may be rendered within a canvas overlaying a...
US-1,025,5081 Method and system for intelligent cloud planning and decommissioning
A method for decommissioning an application operating on a computer system or a computer system includes receiving, at a decommissioning system, information...
US-1,025,5080 Method of providing non-native notifications and system thereof
Embodiments of the present invention are directed to a method of providing non-native notifications and system thereof. These notifications are generated by...
US-1,025,5079 Integrated circuit device including wake-up control circuit and electronic device including the same
An integrated circuit device is provided. The integrated circuit device may include a central processing unit (CPU) configured to operate in one of a plurality...
US-1,025,5078 Operating a pipeline flattener in order to track instructions for complex breakpoints
A semiconductor device comprising a processor having a pipelined architecture and a pipeline flattener and a method for operating a pipeline flattener in a...
US-1,025,5077 Apparatus and method for a hybrid latency-throughput processor
An apparatus and method are described for executing both latency-optimized execution logic and throughput-optimized execution logic on a processing device. For...
US-1,025,5076 Method for performing dual dispatch of blocks and half blocks
A method by a processor for performing multi-dispatch of instruction blocks. The method includes receiving an incoming sequence of instructions, grouping the...
US-1,025,5075 System, method, and computer program product for managing out-of-order execution of program instructions
A method, system and computer program product embodied on a computer-readable medium are provided for managing the execution of out-of-order instructions. The...
US-1,025,5074 Selective flushing of instructions in an instruction pipeline in a processor back to an execution-resolved...
Selective flushing of instructions in an instruction pipeline in a processor back to an execution-determined target address in response to a precise interrupt...
US-1,025,5073 Microcontroller with variable length move instructions using direct immediate addressing or indirect register...
An 8-bit microprocessor has a program memory having a 16-bit instruction word size and a data memory having an 8-bit data size. An instruction word has a...
US-1,025,5072 Architectural register replacement for instructions that use multiple architectural registers
A processor of an aspect includes a decode unit to decode an instruction. The instruction is to explicitly specify a first architectural register and is to...
US-1,025,5071 Method and apparatus for managing a speculative transaction in a processing unit
Method and system for managing a speculative transaction in a processing unit is provided. The speculative transaction is initiated by dispatching a first...
US-1,025,5070 ISA extensions for synchronous coalesced accesses
Global synchrony changes the way computers can be programmed. A new class of ISA level instructions (the globally-synchronous load-store) of the present...
US-1,025,5069 Cleared memory indicator
Aspects include a computer-implemented method for receiving an instruction at a processor, the instruction associated with a memory block having an address. A...
US-1,025,5068 Dynamically selecting a memory boundary to be used in performing operations
A selected boundary of memory to be used in processing an instruction is dynamically selected, based on a predictor. The instruction is decoded, and the...
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