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Patent # Description
US-1,029,7632 Method for an image sensor device
A design method for an image sensor device includes providing an initial design for an image sensor device. The initial design includes a pixel array region and...
US-1,029,7631 Metal block and bond pad structure
In some embodiments, the present disclosure relates to an integrated chip (IC) structure having a conductive blocking structure configured prevent radiation...
US-1,029,7630 Pinned charge transimpedance amplifier
A system that has plural different photodetector circuits, each photodetector circuit including its own transfer gate, and each of the plural different...
US-1,029,7629 Image sensors with in-pixel lens arrays
An image sensor may include an array of pixels. Pixels in the array may include a photodiode that converts incident light into electrical charge and a charge...
US-1,029,7628 Solid-state image pickup device, electronic apparatus, and manufacturing method including various shaped...
A solid-state image pickup device includes: a filter section including filters that are disposed corresponding to respective pixels, and each allowing light of...
US-1,029,7627 Chip scale package for an image sensor
A chip scale package (CSP) structure for an image sensor comprises an image sensor chip, wherein the image sensor chip comprises a semiconductor substrate...
US-1,029,7626 Semiconductor device
A semiconductor device includes a pixel array, a plurality of column circuits, an amplifier, switch arrays of a first layer to an n.sup.th layer, and signal...
US-1,029,7625 Photoelectric conversion device and imaging system
A photoelectric conversion device includes a blocking unit located between a photoelectric conversion layer and a second electrode unit and configured to cause...
US-1,029,7624 Semiconductor device
A reduction is achieved in the power consumption of a solid-state imaging element including a photoelectric conversion element which converts incident light to...
US-1,029,7623 TFT substrate manufacturing method
The present invention provides a TFT substrate manufacturing method. The method uses a photoresist material that contains crystallizable and precipitatable...
US-1,029,7622 Organic light-emitting display device comprising multiple types of thin-film transistors and method of...
An OLED device includes a low-temperature poly-silicon (LTPS) thin-film transistor having a first channel layer, a first gate electrode, a first source...
US-1,029,7621 Transistor substrate and display device
In a transistor substrate of a display device, a plurality of signal lines to which any one of drive signals of a gate signal and a video signal is supplied...
US-1,029,7620 Display device
The disclosed display device includes: a substrate; a gate electrode disposed on the substrate; a first insulating layer disposed on the gate electrode; a metal...
US-1,029,7619 Array substrate
An array substrate includes a substrate, first signal lines, sub-pixels, reference potential lines, first bonding pads, second bonding pads, first fan-out...
US-1,029,7618 Display device
To suppress fluctuation in the threshold voltage of a transistor, to reduce the number of connections of a display panel and a driver IC, to achieve reduction...
US-1,029,7617 Display device and manufacturing method thereof
A display device includes a scan line extending primarily in a first direction, disposed on a substrate, and transmitting a scan signal, a data line extending...
US-1,029,7616 Display panel structure
A display panel includes a gate integrated circuit, a number of scan lines extending from the gate integrated circuit for transmitting scan signals, a source...
US-1,029,7615 Display panel, display device and driving method thereof
The present disclosure discloses a display panel, a display device and a driving method thereof. The display panel comprises: a first substrate and a second...
US-1,029,7614 Gate top spacer for FinFET
The capacitance between gate structures and source/drain contacts of FinFET devices is reduced by the incorporation of inner spacers in the top portions of the...
US-1,029,7613 Method of manufacturing semiconductor device
Reliability of a semiconductor device is improved. Prepared is a substrate in which an insulating layer, a semiconductor layer, and an insulating film are...
US-1,029,7612 Vertical ferroelectric field effect transistor constructions, constructions comprising a pair of vertical...
A vertical ferroelectric field effect transistor construction comprises an isolating core. A transition metal dichalcogenide material encircles the isolating...
US-1,029,7611 Transistors and arrays of elevationally-extending strings of memory cells
A transistor comprises channel material having first and second opposing sides. A gate is on the first side of the channel material and a gate insulator is...
US-1,029,7610 Three-dimensional memory device having on-pitch drain select gate electrodes and method of making the same
An array of memory stack structures extends through an alternating stack of insulating layers and electrically conductive layers over a substrate. An array of...
US-1,029,7609 Flash memory device and manufacture thereof
A flash memory device and its manufacturing method are presented. The flash memory device includes a substrate; a memory unit on the substrate, comprising a...
US-1,029,7608 Inter-digitated capacitor in split-gate flash technology
The present disclosure relates to an integrated chip having an inter-digitated capacitor, and an associated method of formation. In some embodiments, the...
US-1,029,7607 Non-volatile memory having discrete isolation structure and SONOS memory cell, method of operating the same,...
A non-volatile memory having discrete isolation structures and SONOS (Silicon Oxide Nitride Oxide Silicon) memory cells, a method of operating the same, and a...
US-1,029,7606 Gate fringing effect based channel formation for semiconductor device
A memory device is described. Generally, the device includes a string of memory transistors, a source select transistor coupled to a first end of the string of...
US-1,029,7605 Hybrid electronically erasable programmable read-only memory (EEPROM) systems and methods for forming related...
Systems, methods, and techniques described here provide for a hybrid electrically erasable programmable read-only memory (EEPROM) that functions as both a...
US-1,029,7604 Split gate memory devices and methods of manufacturing
Some embodiments of the present disclosure relate to method of forming a memory device. In some embodiments, the method may be performed by forming a floating...
US-1,029,7603 Static random access memory and fabrication method thereof
An SRAM includes a substrate containing a plurality of first substrate regions and a plurality of second substrate regions, a plurality of pull-down transistors...
US-1,029,7602 Implantations for forming source/drain regions of different transistors
A method includes forming a first transistor including forming a first gate stack, epitaxially growing a first source/drain region on a side of the first gate...
US-1,029,7601 Semiconductor devices with layers commonly contacting fins and methods of manufacturing the same
A semiconductor device may include a first active fin, a plurality of second active fins, a first source/drain layer structure, and a second source/drain layer...
US-1,029,7600 Semiconductor device and method of manufacturing the same
A semiconductor device includes a lower electrode on a substrate, a capacitor dielectric layer on the lower electrode, and an upper electrode on the capacitor...
US-1,029,7599 Semiconductor memory device and structure
A semiconductor device, including: a plurality of non-volatile memory cells including a first memory cell and a second memory cell, where the plurality of...
US-1,029,7598 Formation of full metal gate to suppress interficial layer growth
A semiconductor device is provided and has an n-channel field effect transistor (nFET) bottom junction and a p-channel field effect transistor (pFET) bottom...
US-1,029,7597 Composite isolation structures for a fin-type field effect transistor
Structures for the isolation of a fin-type field-effect transistor and methods of forming isolation for a fin-type field-effect transistor. A first dielectric...
US-1,029,7596 Integrated circuit and standard cell library
Provided is an integrated circuit including at least one cell, the at least one cell includes first and second active regions spaced apart from each other, a...
US-1,029,7595 Fin-FET devices and fabrication methods thereof
A method for fabricating a Fin-FET device includes forming a fin structure on a semiconductor substrate having two peripheral regions and a core region, forming...
US-1,029,7594 High density MOSFET array with self-aligned contacts delimited by nitride-capped trench gate stacks and method
A high density trench-gated MOSFET array and method are disclosed. It comprises semiconductor substrate partitioned into MOSFET array area and gate pickup area;...
US-1,029,7593 Semiconductor device
According to one embodiment, a semiconductor device includes a first region having an insulated gate bipolar transistor and a second region having a diode. The...
US-1,029,7592 Monolithic three-dimensional (3D) ICs with local inter-level interconnects
Monolithic 3D ICs employing one or more local inter-level interconnect integrated intimately with at least one structure of at least one transistor on at least...
US-1,029,7591 BiCMOS integration using a shared SiGe layer
A bipolar complementary-metal-oxide-semiconductor (BiCMOS) device is disclosed. The BiCMOS device includes a CMOS device in a CMOS region, a PNP bipolar device...
US-1,029,7590 Electro-static discharge protection device and method of making
The present disclosure teaches a Field-Effect Transistor (FET) configured as a diode to provide ESD protection. The field-effect transistor has its gate,...
US-1,029,7589 Electrostatic discharge and passive structures integrated in a vertical gate fin-type field effect diode
Field effect diode structures utilize a junction structure that has an L-shape in cross-section (a fin extending from a planar portion). An anode is positioned...
US-1,029,7588 Semiconductor device and fabrication method of the same
A semiconductor device includes at least one first gate strip, at least one second gate strip, at least one first conductive line and at least one first...
US-1,029,7587 Integrated circuit
An integrated circuit is provided. In one implementation, the integrated circuit includes a first standard cell, comprising at least one first PMOS transistor...
US-1,029,7586 Methods for processing a 3D semiconductor device
A method for processing a 3D semiconductor device, the method including: providing a wafer including a plurality of first dies, the plurality of first dies...
US-1,029,7585 Multi-resolution compound micro-devices
A compound micro-assembled device comprises a device substrate. A first component having a first native resolution and a second component having a second native...
US-1,029,7584 Chip on board LED device and method
A LED device is disclosed. The device has a LED area, a boundary element surrounding the LED area, a plurality of chip scale package LEDs in the LED area, a...
US-1,029,7583 Semiconductor device package and methods of packaging thereof
An embodiment of the present invention describes a method for forming a doped region at a first major surface of a semiconductor substrate where the first doped...
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