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Searching: cpu processor
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| Patent # | Description |
|---|---|
| US-9,942,179 |
Schedule based execution with extensible continuation based actions Generally in a computing environment, executing work based on time (i.e. according to a predetermined schedule) is a common need. However, in cloud based... |
| US-9,941,007 |
Solid state drive architectures A solid state drive includes DRAM logical flash and flash memory, in which system processor reads and writes only to the DRAM logical flash which minimizes... |
| US-9,935,766 |
Processor and processor system A processor includes a CPU core and an encryption processor which includes an address registration region, wherein, after power is supplied, a startup program... |
| US-9,934,183 |
Server comprising a plurality of modules A server (100) having a plurality of modules (1-8), each module including a communication element (16, 26), a plurality of processors (CPU) (10, 11, 20, 21), a... |
| US-9,929,858 |
Method and system for detecting fault attacks In an embodiment, an integrated circuit (IC) device for detecting fault attacks is disclosed. In the embodiment, the IC device includes a main CPU core, memory... |
| US-9,929,775 |
Techniques for device-to-device communications Embodiments of the present disclosure provide apparatuses and systems for proximity communications. The apparatus may include an integrated circuit (IC) package... |
| US-9,910,801 |
Processor model using a single large linear registers, with new
interfacing signals supporting FIFO-base I/O... A processor or CPU architecture that implements many enabling technologies proven to enhance data through put supporting the synchronous burst data transfer.... |
| US-9,910,770 |
Microcomputer having processor capable of changing endian based on endian
information in memory There is a need to provide a microcomputer capable of eliminating an external terminal for endian selection. Flash memory includes a user boot area for storing... |
| US-9,892,481 |
CPU/GPU synchronization mechanism A thread on one processor may be used to enable another processor to lock or release a mutex. For example, a central processing unit thread may be used by a... |
| US-9,886,735 |
Hybrid engine for central processing unit and graphics processor A method is described for generating procedural textures for a computer having a unified CPU/GPU memory architecture, to generate textures for contents that are... |
| US-9,870,473 |
System and method for security processor control over CPU power states The present disclosure presents methods and apparatuses for controlling a power state, which may include a C-state, of one or more processing cores of a... |
| US-9,866,639 |
Communication apparatus, information processor, communication method, and
computer-readable storage medium According to one embodiment, a communication apparatus communicates with a partner apparatus through a network. The communication apparatus comprises a protocol... |
| US-9,866,572 |
Monitoring use of a sensor of a computing device Monitoring use of a sensor of a computing device. A sensor obtains information from an environment of the computing device. A co-processor provides... |
| US-9,864,979 |
Transaction terminal device When settlement terminal device performs a settlement process with a settlement destination device (for example, an acquirer or a settlement processor),... |
| US-9,864,629 |
Real-time code and data protection via CPU transactional memory suppport A technique allows for memory bounds checking for dynamically generated code by using transactional memory support in a processor. The memory bounds checking... |
| US-9,852,004 |
System and method for parallel processing using dynamically configurable
proactive co-processing cells A parallel processing architecture includes a CPU, a task pool populated by the CPU, and a plurality of autonomous co-processing cells each having an agent... |
| US-9,836,328 |
System and method for improving memory usage in virtual machines at a cost
of increasing CPU usage An apparatus includes at least one processor executing a method for managing memory among a plurality of concurrently-running virtual machines, and a... |
| US-9,830,369 |
Processor for database analytics processing An analytics processing system generates analytics from a collection of unstructured data by. transforming a received source of input data from an unstructured... |
| US-9,830,187 |
Scheduler and CPU performance controller cooperation In one embodiment, an application programming interface (API) is defined that enables a thread scheduler to communicate thread information to the CPU... |
| US-9,830,163 |
Control flow in a heterogeneous computer system Methods, apparatuses, and computer readable media are disclosed for control flow on a heterogeneous computer system. The method may include a first processor of... |
| US-9,824,417 |
Image signal processor for generating depth map from phase detection
pixels and device having the same An image signal processor including a CPU is provided. The CPU receives image data and positional information of phase detection pixels from an imaging device,... |
| US-9,824,166 |
Methods, systems, and computer readable media for utilizing parallel
adaptive rectangular decomposition (ARD)... Methods, systems, and computer readable media for utilizing parallel adaptive rectangular decomposition (ARD) to perform acoustic simulations are disclosed... |
| US-9,818,715 |
Semiconductor integrated circuit device A semiconductor integrated circuit chip, in which multi-core processors are integrated, is usually mounted over an organic wiring board by FC bonding to form a... |
| US-9,817,672 |
Information processing apparatus and method for controlling information
processing apparatus A server computer includes an SDRAM and a service processor that transmits a boot firmware program. The server computer further also includes a CPU that... |
| US-9,811,561 |
Executing database queries using multiple processors A system and a method are disclosed for efficiently executing database queries using a computing device that includes a central processing unit (CPU) and a... |
| US-9,811,380 |
Dynamic allocation of CPU resources based on system load trends Described are techniques for partitioning processors in a system. At a first point in time, a short term workload ratio and a long term workload ratio are... |
| US-9,808,391 |
Walker safety device A safety device for a walker includes a distance measuring sensor for determining whether a user is at too far or too close distances relative to the front side... |
| US-9,800,523 |
Scheduling method for virtual processors based on the affinity of NUMA
high-performance network buffer resources A scheduling method for virtual processors based on the affinity of NUMA high-performance network buffer resources, including: in a NUMA architecture, when a... |
| US-9,800,144 |
Passive component with temperature compensation and electronic device
using the same A passive component with temperature compensation and an electronic device using the same are provided. The electronic device includes a central processor unit... |
| US-9,792,157 |
Execution of an instruction for performing a configuration virtual
topology change In a logically partitioned host computer system comprising host processors (host CPUs) partitioned into a plurality of guest processors (guest CPUs) of a guest... |
| US-9,785,460 |
Dynamic virtual machine sizing A technique is described for managing processor (CPU) resources in a host having virtual machines (VMs) executed thereon. A target size of a VM is determined... |
| US-9,766,924 |
Task processor A task processor includes a CPU, a save circuit, and a task control circuit. A task control circuit is provided with a task selection circuit and state storage... |
| US-9,766,917 |
Limited virtual device polling based on virtual CPU pre-emption A hypervisor executing on a computer system identifies a request of a guest operating system of a virtual machine associated with a shared device. The shared... |
| US-9,760,736 |
CPU obfuscation for cloud applications A cloud deployment system is used for obfuscating CPU operation codes in a set of machines operating in a distributed computing environment. A reprogrammable... |
| US-9,749,207 |
Methods for measuring physical CPU utilization in a cloud computing
infrastructure Novel techniques are provided to determine concurrent hardware resource usage as expressed in activity performed by hardware processors. A cloud computing... |
| US-9,749,189 |
Generating graphical diagram of physical layout of computer platforms In one aspect, a system includes a service processor (SP), having a processor, a non-volatile memory and a communication interface. The SP receives a component... |
| US-9,747,221 |
Dynamic pinning of virtual pages shared between different type processors
of a heterogeneous computing platform A computer system may support one or more techniques to allow dynamic pinning of the memory pages accessed by a non-CPU device, such as a graphics processing... |
| US-9,747,218 |
CPU security mechanisms employing thread-specific protection domains A computer processor includes an instruction processing pipeline that interfaces to a hierarchical memory system employing an address space. The instruction... |
| US-9,746,898 |
Systems and methods for controlling processing device power consumption Systems and methods that may be implemented to decrease power consumption levels of a first processing device (e.g., such as a CPU) based on monitored operating... |
| US-9,746,897 |
Method for controlling a multi-core central processor unit of a device
establishing a relationship between... A method for controlling a central processor unit (CPU) of an electronic device includes establishing a corresponding relationship among operational parameters... |
| US-9,740,866 |
Automatic measuring boot process using an automatic measuring processor
coupled to a memory An apparatus includes a first interface configured to be coupled to a storage device via a first bus. The apparatus includes a second interface configured to be... |
| US-9,740,621 |
Memory controllers employing memory capacity and/or bandwidth compression
with next read address prefetching,... Memory controllers employing memory capacity and/or bandwidth compression with next read address prefetching, and related processor-based systems and methods... |
| US-9,734,549 |
Memory device for providing data in a graphics system and method and
apparatus thereof A central processor unit (CPU) is connected to a system/graphics controller generally comprising a monolithic semiconductor device. The system/graphics... |
| US-9,734,545 |
Software methods in a GPU One embodiment of the present invention sets forth a technique for executing a software method within a graphics processing unit (GPU) that minimizes the number... |
| US-9,734,326 |
Dynamic interrupt stack protection A protection unit of an interrupt stack accessible by a CPU controlled by one software program, for storing and removing stack frame(s), the stack protection... |
| US-9,734,119 |
Systems and methods for accessing vehicle communications bus information
for an application processor The present application discloses a system and method for accessing vehicle communications bus information outside the bandwidth of a limited CPU without... |
| US-9,721,322 |
Selective utilization of graphics processing unit (GPU) based acceleration
in database management A method for the selective utilization of graphics processing unit (GPU) acceleration of database queries in database management is provided. The method... |
| US-9,710,651 |
Secure processor for SoC initialization An embedded system includes an interface to an external peripheral device storing secure boot code and a secure boot controller. The secure boot controller... |
| US-9,697,059 |
Virtualized communication sockets for multi-flow access to message channel
infrastructure within CPU A message channel optimization method and system enables multi-flow access to the message channel infrastructure within a CPU of a processor-based system. A... |
| US-9,680,712 |
Hardware management and control of computer components through physical
layout diagrams In one aspect, a system includes a service processor (SP), having a processor, a non-volatile memory and a communication interface. The SP receives a component... |
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