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Searching: computer memory





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Patent # Description
US-1,016,9252 Configuring functional capabilities of a computer system
Provided is a method for configuring the functional capabilities of a computer system. The computer system may include a persistent memory and a replaceable...
US-1,016,9249 Adjusting active cache size based on cache usage
Provided are a computer program product, system, and method for adjusting active cache size based on cache usage. An active cache in at least one memory device...
US-1,016,9248 Determining cores to assign to cache hostile tasks
Provided are a computer program product, system, and method for determining cores to assign to cache hostile tasks. A computer system has a plurality of cores....
US-1,016,9244 Controlling access to pages in a memory in a computing device
The described embodiments perform a method for handling memory accesses by virtual machines in a computing device. The described embodiments include a reverse...
US-1,016,9241 Managing memory allocation between input/output adapter caches
A first cache of a first IOA is detected storing an amount of data that satisfies a memory shortage threshold. A request for extra memory for the first IOA is...
US-1,016,9238 Memory access for exactly-once messaging
A computer-implemented method is provided for enabling exactly-once messaging. The computer-implemented method includes transmitting a plurality of messages...
US-1,016,9237 Identification of a computing device accessing a shared memory
A method for identifying, in a system including two or more computing devices that are able to communicate with each other, with each computing device having...
US-1,016,9234 Translation lookaside buffer purging with concurrent cache updates
A method and computer processor performs a translation lookaside buffer (TLB) purge with concurrent cache updates. Each cache line contains a virtual address...
US-1,016,9233 Translation lookaside buffer purging with concurrent cache updates
A method and computer processor performs a translation lookaside buffer (TLB) purge with concurrent cache updates. Each cache line contains a virtual address...
US-1,016,9231 Efficient and secure direct storage device sharing in virtualized environments
A method, system and computer program product are disclosed for direct storage device sharing in a virtualized environment. In an embodiment, the method...
US-1,016,9198 Aggregating data for debugging software
A method for obtaining data to debug an issue that affects a software application. In an embodiment, the method includes at least one computer processor...
US-1,016,9196 Enabling breakpoints on entire data structures
Enabling breakpoints on entire data structures include methods, systems, and computer program products for setting breakpoints on a plurality of memory...
US-1,016,9181 Efficient validation of transactional memory in a computer processor
A transactional memory test tests a transactional memory system on a computer processor. A test case with a transactional memory test is constructed such that...
US-1,016,9172 Passive detection of live systems during controller failover in distributed environments
For passive detection of live systems during controller failover in a distributed environment, a set of member systems is sorted according to heartbeat periods...
US-1,016,9157 Efficient state tracking for clusters
Exemplary method, system, and computer program product embodiments for efficient state tracking for clusters are provided. In one embodiment, by way of example...
US-1,016,9153 Reallocation in a dispersed storage network (DSN)
A computing device includes an interface configured to interface and communicate with a dispersed storage network (DSN), a memory that stores operational...
US-1,016,9130 Tailoring diagnostic information in a multithreaded environment
Tailoring diagnostic information specific to current activity of multiple threads within a computer system. A request to dump system state is received. A system...
US-1,016,9129 Dispersed B-tree directory trees
A computing device includes an interface configured to interface and communicate with a dispersed storage network (DSN), a memory that stores operational...
US-1,016,9107 Almost fair busy lock
The present invention provides a method, a system, and a computer program product of preventing thread monitoring preemptions in an almost fair busy lock. In an...
US-1,016,9087 Technique for preserving memory affinity in a non-uniform memory access data processing system
Techniques for preserving memory affinity in a computer system is disclosed. In response to a request for memory access to a page within a memory affinity...
US-1,016,9066 System and method for enhancing advanced driver assistance system (ADAS) as a system on a chip (SOC)
A system on chip (SoC) having an integrated circuit (IC) integrating into a single chip advance driver assistance systems (ADAS) processing unit(s), application...
US-1,016,9025 Dynamic management of software load at customer premise equipment device
Methods, systems, and computer readable media can be operable to facilitate the dynamic management of the software load at a customer premise equipment device....
US-1,016,9014 Compiler method for generating instructions for vector operations in a multi-endian instruction set
A compiler includes a vector instruction processing mechanism that generates instructions for vector instructions in a way that assures correct operation in a...
US-1,016,9010 Performing register promotion optimizations in a computer program in regions where memory aliasing may occur...
Processor hardware detects when memory aliasing occurs, and assures proper operation of the code even in the presence of memory aliasing. Because the hardware...
US-1,016,8961 Hardware transaction transient conflict resolution
In an approach for resolving terminated transactions in a transactional memory environment, a processor initiates a hardware transaction in a computing...
US-1,016,8957 Directed placemat of data in memory
A method of storing computer executable instructions and data elements of a program in a plurality of memory blocks of an embedded system. The method includes...
US-1,016,8954 System and method of interfacing co-processors and input/output devices via a main memory system
A system for interfacing with a co-processor or input/output device is disclosed. According to one embodiment, the system includes a computer processing unit, a...
US-1,016,8950 Coordination of connection initiation scheduling in a distributed storage network (DSN)
A dispersed storage network (DSN) include multiple distributed computing systems distributed across time zones, each including a DSN memory. A global scheduling...
US-1,016,8923 Coherency management for volatile and non-volatile memory in a through-silicon via (TSV) module
An aspect includes coherency management between volatile memory and non-volatile memory in a through-silicon via (TSV) module of a computer system. A plurality...
US-1,016,8922 Volatile and non-volatile memory in a TSV module
An aspect includes data backup management between volatile memory and non-volatile memory in a through-silicon via module of a computer system. Data is copied...
US-1,016,8911 Defragmentation of persistent main memory
Disclosed herein are system, method, and computer program product embodiments for defragmentation of persistent main memory (e.g., storage class memory). An...
US-1,016,8904 Quasi-error notifications in a dispersed storage network
Methods for use in a dispersed storage network (DSN) to retrieve encoded data from memory device of an impaired storage unit. In various examples, a computing...
US-1,016,8890 Document content reordering for assistive technologies by connecting traced paths through the content
Embodiments of the present invention provide a method, system and computer program product for document content re-ordering for assistive technology processing....
US-1,016,8863 Component specifying and selection apparatus and method using intelligent graphic type selection interface
A method generates an output identifying components for a system, each of the components having one of a plurality of types, each of the components defined by a...
US-1,016,8669 Timeline user interface
According to an example aspect of the present invention, there is provided an apparatus comprising at least one processing core, at least one memory including...
US-1,016,7584 Sewing machine
A sewing machine includes a sewing portion, a processor, and a memory. The sewing portion is configured to sew a pattern on a sewing object. The memory storing...
US-1,016,6871 Wheel stability control based on the moment of an electrical motor
A wheel stability control system for an electric vehicle including an electric motor, a drive inverter, and an electronic control unit (ECU) including a...
US-1,016,5736 Autonomous mobile platform and variable rate irrigation method for preventing frost damage
A rover includes a base having wheels and a propulsion system coupled to the wheels to propel the rover around a field. A tower is coupled to the base and...
US-1,016,5393 System for monitoring resource utilization and resource optimization
A system for monitoring resource utilization and optimization includes an entity system having a network communication interface and a memory device storing a...
US-1,016,5137 Image forming apparatus, information display method, and computer-readable recording medium storing program
In an image forming apparatus using a browser with limitation, contents input in an input form cannot be stored in the browser, and thus the contents displayed...
US-1,016,5111 Identifying an unknown contact
For identifying an unknown contact, a system, apparatus, method, and computer program product are disclosed. The apparatus, in one embodiment, includes a...
US-1,016,5045 Information processing apparatus, system, method, and computer readable medium
An information processing apparatus includes: a memory; and a processor coupled to the memory and configured to: receive, from each of a plurality of data...
US-1,016,4941 Cached evaluation of paths through graph-based data representation
Embodiments of the invention generally provide a method, a computing system, and a computer-readable medium configured to request, cache, and generate...
US-1,016,4524 Methods and devices for charge pump level translation in high-speed memory drivers
Embodiments relate to circuits, electronic design assistance (EDA) circuit layouts, systems, methods, and computer readable media to enable logic devices...
US-1,016,3453 Robust voice activity detector system for use with an earphone
An electronic device or method for adjusting a gain on a voice operated control system can include one or more processors and a memory having computer...
US-1,016,3265 Selective light transmission for augmented or virtual reality
One embodiment is directed to a system for enabling two or more users to interact within a virtual world comprising virtual world data, comprising a computer...
US-1,016,3232 Tomographic reconstruction system
A tomography system having a central processing unit, a system memory communicatively connected to the central processing unit, and a hardware acceleration unit...
US-1,016,3227 Image file compression using dummy data for non-salient portions of images
A computer-implemented method is provided for retrieving an image from a user in a desired format and for detecting a compression efficiency for the image. When...
US-1,016,3123 Systems and methods for providing offers using a mobile device
A wireless device is enabled to provide offers. The wireless device receives card data for a financial account card and stores the card data in a memory...
US-1,016,3099 Systems and methods for processing electronic payments using a global payment directory
A computer system for use with a memory device for facilitating electronic payments to a payee from an account associated with a payor is provided. Payor...
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