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Patent # Description
US-1,035,4033 Mapping application functional blocks to multi-core processors
One embodiment provides a system to identify a "best" usage of a given set of CPU cores to maximize performance of a given application. The given application is...
US-1,035,3819 Next line prefetchers employing initial high prefetch prediction confidence states for throttling next line...
Next line prefetchers employing initial high prefetch prediction confidence states for throttling next line prefetches in processor-based system are disclosed....
US-1,033,7914 Sensor for motion information, illumination information and proximity information, and operating method of...
A sensor configured for sensing motion information, illumination information, and proximity information is provided. The sensor includes a light sensing module...
US-1,032,4513 Control of peripheral device data exchange based on CPU power state
A method for processing data includes receiving in a peripheral device, which is connected by a bus to a host processor having host resources, a notification of...
US-1,031,1014 System, method and computer readable medium for offloaded computation of distributed application protocols...
A data processing node includes a management environment, an application environment, and a shared memory segment (SMS). The management environment includes at...
US-1,030,3635 Remote host management using socket-direct network interface controllers
A network adapter includes one or more network ports, multiple bus interfaces, and a processor. The one or more network ports are configured to communicate with...
US-1,030,3143 Numerical controller
A numerical controller of the invention includes a multi-core processor having a plurality of central processing unit (CPU) cores. Herein, importance is...
US-1,029,7239 Electronic wind instrument capable of performing a tonguing process
An electronic wind instrument is provided with a processor (CPU 5) and plural touch sensors (a detecting unit 12s and detecting units 13s) disposed along a...
US-1,029,1673 Transcoding method and system, and distributed file apparatus
A transcoding method used in a computer network comprises: receiving, by a task manager in the computer network, a transcoding task, where the transcoding task...
US-1,028,2300 Accessing physical memory from a CPU or processing element in a high performance manner
A method and apparatus is described herein for accessing a physical memory location referenced by a physical address with a processor. The processor...
US-1,028,1962 Method for CPU/heatsink anti-tip and socket damage prevention
An information handling system (IHS) includes a heatsink retention apparatus. A processor mounted on a board receives a heatsink base having peripheral, spaced...
US-1,026,8504 Interrupt information processing method, virtual machine monitor, and interrupt controller
An interrupt information processing method, a virtual machine monitor, and an interrupt controller. The method includes receiving Q pieces of first interrupt...
US-1,026,1823 Agile VM load balancing through micro-checkpointing and multi-architecture emulation
Methods and systems for agile load balancing include detecting an increased load for a first primary virtual machine (VM) on a first node that has a plurality...
US-1,025,5122 Function callback mechanism between a Central Processing Unit (CPU) and an auxiliary processor
Generally, this disclosure provides systems, devices, methods and computer readable media for implementing function callback requests between a first processor...
US-1,025,5091 Adaptive CPU NUMA scheduling
Systems and methods for performing selection of non-uniform memory access (NUMA) nodes for mapping of virtual central processing unit (vCPU) operations to...
US-1,025,0862 Video processing device
To prevent gradation collapse. A BD player 1 includes a CPU 2 that obtains dynamic range of a monitor, a reproduction section 4 that obtains content...
US-1,024,8595 Virtual machine monitor interrupt support for computer processing unit (CPU)
An interrupt interface of a central processing unit (CPU) comprises a bus with a plurality of interfaces to various components of the CPU. These components can...
US-1,024,8180 Fast SMP/ASMP mode-switching hardware apparatus for a low-cost low-power high performance multiple processor system
A processing system includes multiple processors in which a first processor operates at a first clock frequency and first supply voltage at all times. At least...
US-1,024,8095 Numerical control device having improved servo control performance
A numerical control device includes a multicore CPU for outputting a position command value of a servomotor, an ASIC including a servo controller, which outputs...
US-1,024,3583 CPU error remediation during erasure code encoding
Technology that detects computation errors is disclosed, in which a system may include one or more processors and storage logic. The storage logic may be...
US-1,024,2291 Device for processing images of people, the device seeking to sort these images as a function of contextual...
An image processor device includes a computer processor unit (CPU), at least one memory connected to the CPU, and device for transferring images to the CPU. The...
US-1,023,4932 Method and apparatus for a multiple-processor system
The present disclosure describes methods, systems, and computer program products for a multiple-processor system. The multiple-processor system includes a...
US-1,023,4535 Computer system for measuring real time position of a plurality of animals
The present invention relates to a computer system for measuring real time position of a plurality of animals, which system receives input from a plurality of...
US-1,022,8972 Computer systems and computer-implemented methods for dynamically adaptive distribution of workload between...
In some embodiments, the present invention provides an exemplary computing device, including at least: a scheduler processor; a CPU; a GPU; where the scheduler...
US-1,021,8583 Computing system with off-load processing for networking related tasks
A method is described that comprises executing a service selection method on an off load processor of a computing system to select an available network service...
US-1,021,6655 Memory expansion apparatus includes CPU-side protocol processor connected through parallel interface to...
A memory interface apparatus is provided. The apparatus includes a central processing unit (CPU)-side protocol processor connected to a CPU through a parallel...
US-1,021,6419 Direct interface between graphics processing unit and data storage unit
A system is described that includes a data bus communicatively coupled to a host processor, a graphics processing unit (GPU), and a data storage unit. The GPU...
US-1,021,0114 Interrupt-driven I/O arbiter for a microcomputer system
An I/O (input/output) bus arbiter to be used in conjunction with a compatible CPU (processor) to effect burst mode data transfers in all I/O accesses that...
US-1,021,0088 Computing system with a cache invalidation unit, a cache invalidation unit and a method of operating a cache...
The present application relates to a cache invalidation unit for a computing system having a processor unit, CPU, with a cache memory, a main memory and at...
US-1,019,8251 Processor emulation using multiple translations
Examples described herein emulate a processing architecture using multiple translations of the same source binary. A first translation binary includes compiler...
US-1,018,6007 Adaptive scheduling for task assignment among heterogeneous processor cores
An example system for adaptive scheduling of task assignment among heterogeneous processor cores may include any number of CPUs, a graphics processing unit...
US-1,017,5981 Method to control the number of active vector lanes for power efficiency
The vector data path is divided into smaller vector lanes. The number of active vector lanes is controllable on the fly by the programmer to match the...
US-1,016,8992 Interruptible trigonometric operations
Processor architectures and associated methods provide interruptible, instruction-based trigonometric function computation based on CORDIC iterations, receiving...
US-1,016,2665 Hypervisor assisted control of CPU access to externally managed physical memory
A memory management module receives a request to access a page in a memory, sends the request to a memory controller controlling the memory if the page is...
US-1,016,2658 Virtual processor allocation techniques
One or more virtual processors can be added or removed from a virtual machine based on CPU pressure measured within the virtual machine. In addition to the...
US-1,015,8549 Real-time monitoring of computer system processor and transaction performance during an ongoing performance test
Methods and apparatuses are described for real-time monitoring of computer system processor and transaction performance during an ongoing performance test. A...
US-1,015,2354 Optimized thread scheduling on processor hardware with performance-relevant shared hardware components
To schedule a software thread for execution on a CPU in a multiprocessor system, a scheduler uses both software and hardware utilization information. For a...
US-1,015,2240 Resource allocation based on transaction processor classification
A data transaction processing system including multiple transaction processors also includes a resource allocation system that characterizes the transaction...
US-1,014,0207 Microcomputer having processor capable of changing endian based on endian information in memory
There is a need to provide a microcomputer capable of eliminating an external terminal for endian selection. Flash memory includes a user boot area for storing...
US-1,014,0161 Workload aware dynamic CPU processor core allocation
A method of workload aware dynamic CPU processor core allocation includes the steps of predicting estimated individual workloads for each emulation in a set of...
US-1,014,0151 Leveraging directed acyclic graph (DAG) information to group tasks for execution
Embodiments for leveraging directed acyclic graph (DAG) information to group tasks for execution, by at least one processor device. For a set of tasks, an input...
US-1,013,5928 Network interface device having general-purpose computing capability
Techniques for a network interface controller (NIC) capable of performing general-purpose computing tasks without intervention from a central processing unit...
US-1,012,7039 Extension of CPU context-state management for micro-architecture state
A processor saves micro-architectural contexts to increase the efficiency of code execution and power management. A save instruction is executed to store a...
US-1,012,0773 Estimating processor usage
Methods and systems are disclosed for determining a CPU usage adjustment factor and for automatically applying the CPU usage adjustment factor to provide a CPU...
US-1,011,4679 Logical CPU division usage heat map representation
A logical central processing unit (CPU) division management view is displayed for a device having multiple logical CPU divisions. The management view is...
US-1,010,3956 Virtual machine processor and memory resource coordinator
A network monitor is used to determine resource (e.g., CPU, memory, storage, or network) utilization of one or more virtual machines on one or more...
US-1,010,1977 Method and system of a command buffer between a CPU and GPU
A method and system for a command processor for efficient processing of a program multi-processor core system with a CPU and GPU. The multi-core system includes...
US-1,009,1226 Method and apparatus for service traffic security using DIMM channel distribution in multicore processing system
The present invention relates to a multicore communication processing service. More specifically, aspects of the present invention provide a technology for...
US-1,008,9150 Apparatus, device and method for allocating CPU resources
A method of central processor unit (CPU) resource allocation for a multi-processor device includes the step of obtaining the amounts of demanded CPU resources...
US-1,008,3145 Motherboard module having switchable PCI-E lane
A motherboard module having switchable PCI-E lanes includes a CPU, a first PCI-E slot, a second PCI-E slot, a first switch, and a second switch. 1st to a-th...
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