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Searching: cpu processor





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Patent # Description
US-6,199,118 System and method for aligning an initial cache line of data read from an input/output device by a central...
A computer is provided having a bus interface unit coupled between a CPU bus, a PCI bus and/or a graphics bus. The bus interface unit includes controllers linked...
US-6,198,629 Circuit board and computer system for enhanced cooling
A computer system including a chassis of substantially rectangular cross section suitable for receiving a circuit board. A rear face of the chassis includes...
US-6,196,919 Shooting game apparatus, method of performing shooting game, and computer-readable recording medium storing...
A CPU of a control system controls a signal processor to effect various calculations to move a player's spaceship on a projection display screen, orient the...
US-6,195,750 Method and apparatus for dynamic CPU reconfiguration in a system employing logical processors
A multiprocessor system having a plurality of CPUs that can be dynamically reconfigured between online and offline without system shutdown. The multiprocessor...
US-6,195,739 Method and apparatus for passing data among processor complex stages of a pipelined processing engine
A processor complex architecture facilitates accurate passing of transient data among processor complex stages of a pipelined processing engine. The processor...
US-6,193,152 Modular signature and data-capture system and point of transaction payment and reward system
A modular signature and data capture device employs a standardized ISA bus, standardized communication ports, and standardized x86 CPU architecture to promote...
US-6,189,052 On-chip i/o processor supporting different protocols having on-chip controller for reading and setting pins,...
An on-chip i/o-processor for controlling and communication with peripheral devices, wherein an i/o processor core (12), comprising at least one pin controller...
US-6,185,597 Method and system for expanding a buried stack frame
A method and system for growing stack frames is described. According to the invention, actual growth of a stack frame buried below the top of the stack is...
US-6,184,908 Method and apparatus for co-processing video graphics data
To minimize CPU processing requirements for preparing and transferring data to a graphics processor, a graphics command processor is provided that supports...
US-6,178,465 Image processors for reading and outputting data
An image processor which reads and outputs image data. Only by inputting a keyword which causes us to associate an image intuitively, the image processor...
US-6,175,889 Apparatus, method and system for a computer CPU and memory to high speed peripheral interconnect bridge having...
A core logic chip set in a computer system provides a bridge between processor host and memory buses and a plurality of registered peripheral component...
US-6,175,880 Sound board emulation using digital signal processor
An improved audio-output device coupleable to a computer system, in which a DSP operating under software control emulates a common command interface. The command...
US-6,173,416 System and method for detecting errors using CPU signature
A fault-tolerant computer architecture is described wherein the effect of hardware faults is diminished. The architecture employs a main data bus having a...
US-6,173,409 Real-time power conservation for electronic device having a processor
A real-time power conservation apparatus and method for portable computers employs a monitor to determine whether a CPU may rest based upon a real-time sampling...
US-6,173,366 Load and store instructions which perform unpacking and packing of data bits in separate vector and integer...
A multimedia extension unit (MEU) is provided for performing various multimedia-type operations. The MEU can be coupled either through a coprocessor bus or a...
US-6,173,358 Computer system having dual bus architecture with audio/video/CD drive controller/coprocessor having integral...
A computer system for high-performance video and audio manipulations comprising a locked memory cartridge and an audio/video/compact disk (CD) drive...
US-6,172,990 Media access control micro-RISC stream processor and method for implementing the same
Disclosed are methods and apparatus for processing packet data received from a physical layer. The processing is performed in-line while streaming packets to an...
US-6,169,892 Flow control of authentication triplet request for reducing usage time of a central processor
A method of requesting authentication triplets as a function of CPU processing time at a MSC. The MSC requests a new set of authentication triplets from an HLR...
US-6,167,509 Branch performance in high speed processor
A high-performance CPU of the RISC (reduced instruction set) type employs a standardized, fixed instruction size, and permits only simplified memory access data...
US-6,163,851 Data processor
A data processor including an alternative clock generator for generating, in a power saving mode, an alternative clock signal which is supplied to a peripheral...
US-6,163,829 DSP interrupt control for handling multiple interrupts
A multi-processor system is provided having a processor array configured of a plurality of CPUs (20) that are disposed on a global bus (14). A VEM interface (18)...
US-6,161,162 Multiprocessor system for enabling shared access to a memory
A multiprocessing computer system and method providing multiplexed address and data paths from multiple CPUs to a single storage device. These paths are...
US-6,161,159 Multimedia computer with integrated circuit memory
An alternate route to improved multimedia performance without replacing the central processor unit (CPU) is presented, through the utilization of general-purpose...
US-6,158,656 Final accommodation device for power-source drop
A method and apparatus for enabling a processor to execute processing routine even if a power-source voltage drop occurs during processing. When an ignition key...
US-6,158,023 Debug apparatus
The present invention provides a debug apparatus that can set complex break conditions, minimize a time lag from the detection of a break event to the break an...
US-6,158,020 Remote jumper set and reset
A client on a network is provided with auxiliary low power logic, at the network adapter, that is always active and simulates network traffic (e.g. Ethernet...
US-6,157,984 Integrated controller/processor for disc drive having direct memory access
A single chip integrated disc/servo controller and processor (CPU) for a disc drive reduces timing overhead associated with processor/controller/memory...
US-6,157,967 Method of data communication flow control in a data processing system using busy/ready commands
A multiprocessor system includes a number of sub-processor systems, each substantially identically constructed, and each comprising a central processing unit...
US-6,157,397 AGP read and CPU wire coherency
A method for graphics device read and processor write coherency receives a write request from a processor to write data to a storage element for a component to...
US-6,154,831 Decoding operands for multimedia applications instruction coded with less number of bits than combination of...
A multimedia extension unit (MEU) is provided for performing various multimedia-type operations. The MEU can be coupled either through a coprocessor bus or a...
US-6,154,830 Microprocessor
On a microprocessor chip mounting a central processing unit (CPU) for controlling the entire operation of electronic equipment and a digital signal processor...
US-6,154,827 Data processor capable of high speed accessing
A data processor capable of accessing data with the data processing capacity of a central processing unit (CPU), even if the data processing capacity of the CPU...
US-6,154,785 Inter-processor communication system
An inter-processor communication system for a multi-processor environment wherein each processor has an associated processor system controller comprising an...
US-6,151,689 Detecting and isolating errors occurring in data communication in a multiple processor system
A multiprocessor system includes a number of sub-processor systems, each substantially identically constructed, and each comprising a central processing unit...
US-6,147,863 Industrial computer
An industrial computer including a passive backplane generally compliant with the PCI/ISA industrial standard promulgated by the PICMG technical committee, but...
US-6,145,102 Transmission of an error message over a network by a computer which fails a self-test
A computer may have a management bus installed, where the management bus is coupled to sensors which monitor status of components of the computer. The management...
US-6,145,100 Debug interface including timing synchronization logic
A system for debugging a processor includes a logic circuit for communicating commands and data between an input/output port which operates at a first clock...
US-6,144,460 Data processing method, and data processor and printer using data processing method
A data processing method which efficiently performs data transfer by using a data bus with an appropriate access width corresponding to transfer data and a...
US-6,144,322 Variable length code processor with encoding and/or decoding
A variable length code processor is obtained which can perform encoding or decoding process in a plurality of variable length encoding standards. A sequence...
US-6,141,673 Microprocessor modified to perform inverse discrete cosine transform operations on a one-dimensional matrix of...
A multimedia extension unit (MEU) is provided for performing various multimedia-type operations. The MEU can be coupled either through a coprocessor bus or a...
US-6,141,306 Optical disc drive and methods of examining the optical disc drive
An optical disc drive for recording and playing back a recordable-type optical disc includes a driving mechanism for rotating the optical disc, an optical...
US-6,134,308 Caller ID logging: entry storage on a per line basis
A telephone system with a caller ID logging feature includes a plurality of telephone stations which share a plurality of telephone lines connected to the...
US-6,130,898 Simulcasting digital video programs for broadcast and interactive services
To provide interactivity, a public wireless packet data network is combined with a broadband digital broadcast network. In the preferred embodiment, the...
US-6,128,763 Dynamically changing forward error correction and automatic request for repetition
A transceiver device having a forward error correction decoder providing at least one forward error correction metric and a data integrity monitor providing at...
US-6,128,702 Integrated processor/memory device with victim data cache
An integrated processor/memory device comprising a main memory, a CPU, a victim cache, and a primary cache. The main memory comprises main memory banks. The...
US-6,124,865 Duplicate cache tag store for computer graphics system
A duplicate cache tag store, accessible to a graphics processor and to devices connected to the I/O bus without creating traffic on the system bus. Any entry...
US-6,122,716 System and method for authenticating a computer memory
A computer system for high-performance video and audio manipulations comprising a locked memory cartridge and an audio/video/compact disk (CD) drive...
US-6,122,713 Dual port shared memory system including semaphores for high priority and low priority requestors
A system and method for controlling access to a dual port shared memory in a system comprising a host computer system and a communication device comprised in or...
US-6,122,699 Data processing apparatus with bus intervention means for controlling interconnection of plural busses
This invention has as its object to improve the net processing speed by appropriately assigning the DMA processing time for attaining high-speed processing using...
US-6,122,696 CPU-peripheral bus interface using byte enable signaling to control byte lane steering
A CPU-Peripheral bus interface for 64-bit local bus to 32-bit peripheral bus uses byte enable signaling to provide byte lane steering. Qbuffer logic provides a...
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